Patents by Inventor Martin Carroll
Martin Carroll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11928112Abstract: Systems and methods are provided that use a trained process to reply to a request comprising query data defining a query and context data defining contextual factors for the query from a device. The query is answered by one or more selected APIs of a plurality of APIs that invoke respective services to prepare a response. The trained process determines an execution plan responsive to the query data and the context data and is configured using training to define execution plans comprising selected APIs where a particular API is selected for the plan if it answers at least a portion of the query and the selected APIs together prepare the response optimized for the device according to the context data. The plan is provided to an execution component to execute the plan using the selected APIs and send the response to the requesting device.Type: GrantFiled: April 23, 2021Date of Patent: March 12, 2024Assignee: The Toronto-Dominion BankInventors: Milos Dunjic, Martin Albert Lozon, David Samuel Tax, Arthur Carroll Chow, Peter Glen Nairn, Edward James Hood, John Jong-Suk Lee, Arun Victor Jagga
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Patent number: 11473131Abstract: The presently disclosed subject matter provides high-throughput methods for performing genomic DNA methylation assessments. The presently disclosed subject matter further provides methods for diagnosing a subject with a disease and/or disorder, and for determining the prognosis of a subject that has a disease and/or disorder. In certain embodiments, the present disclosure provides a diagnostic method that includes obtaining a biological sample from the subject; determining the methylation status of one or more genomic DNA loci in one or more cells of the biological sample; and diagnosing a disease and/or disorder in the subject, wherein the methylation status of the one or more genomic DNA loci indicates the presence of the disease and/or disorder in the subject.Type: GrantFiled: August 21, 2015Date of Patent: October 18, 2022Assignee: THE TRUSTEES OF THE UNIVERSITY OF PENNSYLVANIAInventors: Martin Carroll, Stephen Master, Gerald Wertheim, Marlise Luskin
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Patent number: 9852939Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.Type: GrantFiled: January 30, 2013Date of Patent: December 26, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe
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Patent number: 9852940Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.Type: GrantFiled: January 31, 2013Date of Patent: December 26, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe
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Publication number: 20170275686Abstract: The presently disclosed subject matter provides high-throughput methods for performing genomic DNA methylation assessments. The presently disclosed subject matter further provides methods for diagnosing a subject with a disease and/or disorder, and for determining the prognosis of a subject that has a disease and/or disorder. In certain embodiments, the present disclosure provides a diagnostic method that includes obtaining a biological sample from the subject; determining the methylation status of one or more genomic DNA loci in one or more cells of the biological sample; and diagnosing a disease and/or disorder in the subject, wherein the methylation status of the one or more genomic DNA loci indicates the presence of the disease and/or disorder in the subject.Type: ApplicationFiled: August 21, 2015Publication date: September 28, 2017Inventors: Martin Carroll, Stephen Master, Gerald Wertheim, Marlise Luskin
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Publication number: 20140009576Abstract: In one embodiment, the method includes receiving at least one tile of a current frame of video data. The method further includes determining whether the tile is a static tile or a dynamic tile based on the current frame and a corresponding tile in an earlier frame. The method further includes partitioning pixels of a static tile into at least one bin, the number of bins being greater than the number of color values that were permitted for the corresponding tile in the earlier frame. The static tile is a tile that has not changed from the earlier frame. The method further includes partitioning pixels of a changed tile into at least one bin, the number of bins being less than the number of color values that were permitted for the corresponding tile in the earlier frame. The changed tile is a tile that has changed from the earlier frame.Type: ApplicationFiled: July 5, 2012Publication date: January 9, 2014Applicant: ALCATEL-LUCENT USA INC.Inventors: Ilija Hadzic, Hans Woithe, Martin Carroll
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Patent number: 8536645Abstract: According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.Type: GrantFiled: February 21, 2011Date of Patent: September 17, 2013Assignee: International Rectifier CorporationInventors: Timothy D. Henson, Ling Ma, Hugo Burke, David P. Jones, Martin Carroll
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Patent number: 8368211Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.Type: GrantFiled: November 5, 2004Date of Patent: February 5, 2013Assignee: International Rectifier CorporationInventors: Martin Standing, Andrew Sawle, Matthew P Elwin, David P Jones, Martin Carroll, Ian Glenville Wagstaffe
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Publication number: 20120211825Abstract: According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.Type: ApplicationFiled: February 21, 2011Publication date: August 23, 2012Applicant: INTERNATIONAL RECTIFIER CORPORATIONInventors: Timothy D. Henson, Ling Ma, Hugo Burke, David P. Jones, Martin Carroll
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Patent number: 8143729Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.Type: GrantFiled: January 26, 2009Date of Patent: March 27, 2012Assignee: International Rectifier CorporationInventors: Mark Pavier, Danish Khatri, Daniel Cutler, Andrew Neil Sawle, Susan Johns, Martin Carroll, David Paul Jones
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Patent number: 8125083Abstract: A semiconductor device includes a die with at least one electrode on a surface thereof, at least one solderable contact formed on the electrode, and a passivation layer formed over the electrode and including an opening that exposes the solderable contact. The passivation layer opening may be wider than the solderable contact such that a gap extends between the contact and the passivation layer. The device also includes a barrier layer disposed on the top surface of the electrode, and along the underside of the solderable contact and across the gap. The barrier layer may also extend under the passivation layer and may cover the entire top surface of the electrode. The barrier layer may also extend along the sidewalls of the electrode. The barrier layer may include a titanium layer or a titanium layer and nickel layer. The barrier layer protects the electrode and underlying die from acidic fluxes found in lead-free solders.Type: GrantFiled: September 5, 2006Date of Patent: February 28, 2012Assignee: International Rectifier CorporationInventors: Martin Carroll, David P. Jones, Andrew N. Sawle, Martin Standing
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Publication number: 20090218684Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.Type: ApplicationFiled: January 26, 2009Publication date: September 3, 2009Inventors: Mark Pavier, Danish Khatri, Daniel Cutler, Andrew Neil Sawle, Susan Johns, Martin Carroll, David Paul Jones
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Publication number: 20070052099Abstract: A semiconductor device includes a die with at least one electrode on a surface thereof, at least one solderable contact formed on the electrode, and a passivation layer formed over the electrode and including an opening that exposes the solderable contact. The passivation layer opening may be wider than the solderable contact such that a gap extends between the contact and the passivation layer. The device also includes a barrier layer disposed on the top surface of the electrode, and along the underside of the solderable contact and across the gap. The barrier layer may also extend under the passivation layer and may cover the entire top surface of the electrode. The barrier layer may also extend along the sidewalls of the electrode. The barrier layer may include a titanium layer or a titanium layer and nickel layer. The barrier layer protects the electrode and underlying die from acidic fluxes found in lead-free solders.Type: ApplicationFiled: September 5, 2006Publication date: March 8, 2007Inventors: Martin Carroll, David Jones, Andrew Sawle, Martin Standing
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Publication number: 20060209825Abstract: A processing device, configured to implement at least a portion of a scheduled medium-access protocol (SMAP) in a communication system, comprises a processor, a memory coupled to the processor, and one or more additional hardware modules. The functionality of the portion of the SMAP implemented in the processing device is partitioned between software, stored in the memory and executable by the processor, and hardware comprising the one or more additional hardware modules. In an illustrative embodiment, the processing device comprises a head-end device of a passive optical network, and the functionality comprises at least a scheduler and a grant generator, with the scheduler being implemented in the software and the grant generator being implemented in the hardware.Type: ApplicationFiled: March 16, 2005Publication date: September 21, 2006Inventors: Martin Carroll, Ilija Hadzic, Dusan Suvakovic
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Publication number: 20050269677Abstract: A semiconductor device which includes a power electrode on a surface thereof, a solderable body on the power electrode and a passivation body spaced from but surrounding the solderable body.Type: ApplicationFiled: May 26, 2005Publication date: December 8, 2005Inventors: Martin Standing, Andrew Sawle, David Jones, Martin Carroll, Matthew Elwin
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Publication number: 20050200011Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.Type: ApplicationFiled: November 5, 2004Publication date: September 15, 2005Inventors: Martin Standing, Andrew Sawle, Matthew Elwin, David Jones, Martin Carroll, Ian Wagstaffe
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Patent number: 6898147Abstract: The invention comprises a system for processing seismic data to estimate time shift resulting from velocity anisotropy in the earth's subsurface. A gather of seismic data traces is formed and selected seismic data traces included in said gather within selected time windows are cross-correlated to estimate the time shift in the seismic data traces included in said gather resulting from velocity anisotropy in the earth's subsurface.Type: GrantFiled: October 20, 2003Date of Patent: May 24, 2005Assignee: Input/Output, Inc.Inventors: Edward Louis Jenner, Martin Carroll Williams
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Patent number: 6681184Abstract: The invention comprises a system for processing seismic data to estimate time shift resulting from velocity anisotropy in the earth's subsurface. A gather of seismic data traces is formed and selected seismic data traces included in said gather within selected time windows are cross-correlated to estimate the time shift in the seismic data traces included in said gather resulting from velocity anisotropy in the earth's subsurface.Type: GrantFiled: May 15, 2001Date of Patent: January 20, 2004Assignee: Input/Output, Inc.Inventors: Edward Louis Jenner, Martin Carroll Williams
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Publication number: 20030018435Abstract: The invention comprises a system for processing seismic data to estimate time shift resulting from velocity anisotropy in the earth's subsurface. A gather of seismic data traces is formed and selected seismic data traces included in said gather within selected time windows are cross-correlated to estimate the time shift in the seismic data traces included in said gather resulting from velocity anisotropy in the earth's subsurface.Type: ApplicationFiled: May 15, 2001Publication date: January 23, 2003Inventors: Edward Louis Jenner, Martin Carroll Williams
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Patent number: D687080Type: GrantFiled: October 5, 2012Date of Patent: July 30, 2013Inventor: Martin Carroll