Abstract: A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide material may also be formed on the top surface of wordlines adjacent the active regions during the selective silicidation process. A single nitride insulating layer is used, and portions of the workpiece are covered with photoresist during the formation of the silicide material.

Abstract: A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide material may also be formed on the top surface of wordlines adjacent the active regions during the selective silicidation process. A single nitride insulating layer is used, and portions of the workpiece are covered with photoresist during the formation of the silicide material.

Abstract: Disclosed is an optical lithographic mask having one or more dummy patterns, each said dummy pattern having a masked area of said optical lithographic mask separated from one or more feature masked areas on said optical lithographic mask by an unmasked region of width d, wherein said width d is selected to substantially minimize an average deviation between the dimensions of said feature masked areas and corresponding features etched out upon a semiconductor surface utilizing said optical lithographic mask.

Abstract: A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.

Abstract: A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.

Abstract: A semiconductor wafer structure in a overlay pattern that permits determination of overlay and critical dimension features by CD SEM in a single pass along a given axis, comprising: a) a center feature section that provides a critical dimension point along a given axis; b) plurality of smaller sections positioned adjacent to the center feature section along the given axis that include a plurality of spaces between each of the plurality of smaller sections; and c) a plurality of displacement lines adjacent to the plurality of the smaller sections to displace a plurality of spaces.