Abstract: A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

Abstract: A method and circuit arrangement is provided for controlling switching transistors of an integrated circuit, with a bridge circuit and with a control unit, which is designed and/or has a program so that the control unit is designed as a measuring device and measures a bridge voltage of the bridge circuit, outputs an adjusting signal for adjusting a component of a bridge circuit, and outputs a control signal for activating the switching transistors. When the bridge circuit) has a branch with a resistor network and a transistor connected in series, and the control unit is designed and/or has a program so that the adjusting signal for adjusting a resistance value of the resistor network is switchable as the component dependent on the bridge voltage.

Abstract: A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS1) and a first operating potential (VDD1) in a second operating voltage range (II) having a second ground potential (VSS2) and a second operating potential (VDD2), having an input circuit to which the input signal (in) may be applied and an output circuit at which the output signal (out) may be picked off, the input circuit having at least one native transistor.

Abstract: A level shifter for converting an input signal (in) from a first operating voltage range (I) having a first ground potential (VSS1) and a first operating potential (VDD1) into an output signal (out) in a second operating voltage range (II) having a second ground potential (VSS2) and a second operating potential (VDD2). An input circuit (1) receives the input signal and an output circuit (2) provides the output signal (out), where the input circuit includes a parallel circuit made up by a first cascode circuit and a second cascode circuit, and the first and second cascode circuits each being formed by a first transistor in the source circuit and a second transistor in the gate circuit, a dynamic control being provided for the second transistors.

Abstract: The invention relates to a level slider circuit having a first level slider (1) and a second level slider (2) switched in series for the conversion of an input signal (Vin) from a first operating voltage range (A) at a first ground voltage (VSSA) and a first supply voltage (VDDA) into an output signal (Vout) in a second operating voltage range (B) at a second ground voltage (VSSB) and a second supply voltage (VDDB), wherein the first level slider (1) is embodied for the conversion of the input signal (Vin) to the ground voltage (VSSA) of the second operating voltage range (B) for the conversion of the input signal (Vin), and that the second level slider (2) is embodied for the conversion of an intermediate signal (VZ) output by the first level slider (1) to the output signal travel (?Vout).

Abstract: A circuit with protection against electrostatic destruction comprises at least two sections (A, B) composed of a first and second section (A, B). Each of the sections (A, B) has its own working voltage system with a fundamental voltage (USS or USS1) and a supply voltage (UDD or UDD1), and at least one connection (SC) between an information terminal (SA) of the first section (A) and an information terminal (SB) of the second section (B) to transfer information between the first section (A) and the second section (B). The connection (SC) has a transistor circuit with at least one transistor (X) of the first section (A), a resistance (R1), and a first transistor (E) of the second section (B), wherein the first transistor (X) is connected between the fundamental voltage (USS) of the first section (A) and the resistance (R1), and the first transistor (E) of the second section (B) is connected between the resistance (R1) and the supply voltage (UDD1) of the second section (B).

Abstract: The invention relates to a testing method and to a test circuit arrangement for testing a circuit section of a circuit, having a connection section connected to the circuit section used to conduct a current from or to the circuit section, and having a detector circuit; wherein a first tapping point is arranged on the connection section at a distance from a transition to the circuit section, a second tapping point is arranged at the connection section that is closer to the circuit section than the first tapping point, and wherein the detector circuit samples a voltageor a voltage-equivalent value between the first and the second tapping point for testing of the circuit section.

Abstract: An integrated circuit includes at least two circuit components formed on a common semiconductor substrate. Each circuit component has a self-contained supply voltage system. Coupling circuits couple the supply voltage systems for the at least two circuit components. Each coupling circuit includes at least one transistor having a base formed by or within the substrate itself; more specifically, by or within a region of the substrate contiguous with collector doping zones and emitter doping zones of the transistor. The resistance between the transistor base and the potentials of the two supply voltage systems coupled by each of the coupling circuits is the intrinsic resistance of the substrate between the region forming the base and one of each contact doping zone conductively connected to the collector or emitter through a metallization applied to the substrate.

Abstract: A circuit with protection against electrostatic destruction comprises at least two sections (A, B) composed of a first and second section (A, B). Each of the sections (A, B) has its own working voltage system with a fundamental voltage (USS or USS1) and a supply voltage (UDD or UDD1), and at least one connection (SC) between an information terminal (SA) of the first section (A) and an information terminal (SB) of the second section (B) to transfer information between the first section (A) and the second section (B). The connection (SC) has a transistor circuit with at least one transistor (X) of the first section (A), a resistance (R1), and a first transistor (E) of the second section (B), wherein the first transistor (X) is connected between the fundamental voltage (USS) of the first section (A) and the resistance (R1), and the first transistor (E) of the second section (B) is connected between the resistance (R1) and the supply voltage (UDD1) of the second section (B).

Abstract: A circuit for level shifting comprises a first and second transistor (A, B), to each of which a signal can be applied, and a third and fourth transistor (C, D). The first and third transistors (C, D) are connected between a fundamental voltage (XUSS) and a supply voltage (XUDD) and have between them a first connection point (O1). The second and fourth transistors (B, D) are connected between the fundamental voltage (XUSS) and the supply voltage (XUDD), and have between them a second connection point (O2). The first connection point (O1) is connected to apply a control signal to the fourth transistor (D) at its control terminal, and the second connection point (O2) is connected to apply a control signal to the third transistor (C) at its control terminal. The circuit is characterized by at least one amplifier circuit (V) to amplify at least one of these control signals.

Abstract: The invention relates to a circuit arrangement with two or more circuit sections, which cooperate through a data transfer device. The invention solves the problem of double area expenditure for two memory devices for each receiver, in that the data bus itself takes over the role of one of these memory devices, namely that of the memory device functioning as master. For this it is only necessary to integrate a single memory device on the data bus, which takes over the role of the no longer needed memory device for each data receiver. By saving the memory device associated with each receiver, the semiconductor chip area needed for communication buses can be optimized and the master memory device of the prior art may be replaced by the bus capacitance.

Abstract: To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

Abstract: An integrated circuit has at least two circuit components (1, 2), which are formed on a semiconductor substrate (13) of a first conductivity type and each of which has a self-contained supply voltage system; the integrated circuit has at least one coupling circuit which connects the same potentials (Vss1, Vss2; Vcc1, Vcc2) of the two supply voltage systems in such a way as to intercept the voltage peaks. The coupling circuit includes at least one transistor (T1, T2, T3) with a base (20, 21, 22) of the first conductivity type, and a collector (15, 16, 17, 18) and emitter (15, 16, 17, 18) of a second conductivity type, the base of which transistor is connected through a resistor (R) to the potentials (Vss1, Vss2) of the two supply voltage systems, and the collector and emitter of which are directly connected to one of these potentials.

Abstract: An electrostatic discharge (ESD) protective structure is configured to protect an integrated circuit, which is connected between a first voltage bus with a first supply voltage and a second voltage bus with a second supply voltage. The ESD protective structure includes a plurality of laterally designed bipolar transistors, whose load lines are arranged parallel to one another and between the voltage buses, and whose control connections are connected to one of the voltage buses. A resistor track is disposed in the load line of each bipolar transistor and is co-integrated into the ESD protective structure on the collector side and/or the emitter side.

Abstract: An electrostatic discharge (ESD) protective structure is configured and arranged to protect an integrated semiconductor circuit that is located between a first potential bus with a first supply potential and a second potential bus with a second supply potential. The ESD protective structure includes a laterally shaped ESD diode having a first region with a first conduction type and a second region of a second conduction type spaced apart from the first region. The ESD protective structure is located between the potential busses and is provided with a gate electrode, such that the first region and the second region are adjusted with respect to the gate electrode, and the spacing between the first region and the second region corresponds to the length of the gate electrode.

Abstract: An electrostatic discharge (ESD) protective structure is configured to protect an integrated circuit, which is connected between a first voltage bus with a first supply voltage and a second voltage bus with a second supply voltage. The ESD protective structure includes a plurality of laterally designed bipolar transistors, whose load lines are arranged parallel to one another and between the voltage buses, and whose control connections are connected to one of the voltage buses. A single track resistor is co-integrated into the semiconductor body and precedes every control connection of the bipolar transistors.

Abstract: To protect against electrostatic discharges in monolithic integrated circuits in CMOS technology, a lateral thyristor structure is presented which has a much lower firing voltage compared to conventional thyristor structures.

Abstract: The invention relates to a circuit arrangement with two or more circuit sections, which cooperate through a data transfer device. The invention solves the problem of double area expenditure for two memory devices for each receiver, in that the data bus itself takes over the role of one of these memory devices, namely that of the memory device functioning as master. For this it is only necessary to integrate a single memory device on the data bus, which takes over the role of the no longer needed memory device for each data receiver. By saving the memory device associated with each receiver, the semiconductor chip area needed for communication buses can be optimized.