Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Abstract: A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes.

Abstract: A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes.

Abstract: A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70). The parallel registers (72)-(80) are individually addressable by an address decoder (104) for storage of test vectors therein. These test vectors are then applied to associated logic circuits. Individual shift register latches (92)-(102) are provided at imbedded locations therein. The shift register latches are interfaced with a serial data link to allow serial loading of data therein. The parallel latches function in both the test mode to store test vectors for application to the associated logic and also in the operational mode for storage of logic data. Use of parallel registers increases the speed at which data is scanned into the device.

Abstract: A logic circuit that has a plurality of stages that are driven by a clock source that provides at least 2 clock signals and includes at least a single latch stage located between two of the plurality of stages is configured with field effect transistor technology. The latch stage includes an isolation means for isolating the preceding circuit of the plurality of stages from flow-through of the clocks and signals that are connected to the latch stage, and a latch circuit for storing the data that is applied to the latch stage between clock pulses. A plurality of latch stages can easily be configured as a shift register latch.