Abstract: A method and apparatus for high speed asynchronous serial data transfer between two microprocessors. Each of the two microprocessors is coupled to an asynchronous receiver/transmitter having a request-to-send output and a clear-to-send input. Each asynchronous receiver/transmitter also has a wait/ready output for utilization in conjunction with direct memory access devices or processors. The wait/ready output of a first asynchronous receiver/transmitter is applied to a digital filter to remove transients therein and the filtered signal is then coupled to the clear-to-send input of a second asynchronous receiver/transmitter, enabling the second asynchronous receiver/transmitter to transmit data back to the first asynchronous receiver/transmitter.