Abstract: A Schottky diode and a method of manufacturing the Schottky diode are disclosed. The Schottky diode has an N-well or N-epitaxial layer with a first region, a second region substantially adjacent to an electron doped buried layer that has a donor electron concentration greater than that of the first region, and a third region substantially adjacent to the anode that has a donor electron concentration that is less than that of the first region. The second region may be doped with implanted phosphorus and the third region may be doped with implanted boron.

Abstract: A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region.

Abstract: In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.

Abstract: The present technology is related generally to vertical discrete devices with a trench at the topside of the vertical discrete devices. The trench is filled with a conducting material. In this approach, a drain or cathode of the vertical discrete devices is electrically connected to the topside to result in a small area with low RON*AREA.

Abstract: The present technology is related generally to vertical discrete devices with a trench at the topside of the vertical discrete devices. The trench is filled with a conducting material. In this approach, a drain or cathode of the vertical discrete devices is electrically connected to the topside to result in a small area with low RON*AREA.

Abstract: A Schottky diode and a method of manufacturing the Schottky diode are disclosed. The Schottky diode has an N-well or N-epitaxial layer with a first region, a second region substantially adjacent to an electron doped buried layer that has a donor electron concentration greater than that of the first region, and a third region substantially adjacent to the anode that has a donor electron concentration that is less than that of the first region. The second region may be doped with implanted phosphorus and the third region may be doped with implanted boron.

Abstract: A floorplan for a die having three high-voltage transistors for power applications is described. The three high-voltage transistors are specifically placed in relation to each other to optimize operation.

Abstract: In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.

Abstract: A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.

Abstract: A method for fabricating a bipolar transistor includes forming a first region of a first conductivity type in a semiconductor structure to form a collector region and forming a second region of a second conductivity type in the first region to form a base region. A first mask is applied including an opening defining an emitter region of the bipolar transistor. The method further includes a triple implantation process using the first mask. Thus, a third region of the first conductivity type is formed in the first region and overlaid the second region. A fourth region of the second conductivity type is formed in the second region and is more heavily doped than the second region. A fifth region of the first conductivity type is formed in the second region and above the fourth region. The fifth region forms the emitter region of the bipolar transistor.

Abstract: A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.

Abstract: A method for fabricating a bipolar transistor includes forming a first region of a first conductivity type in a semiconductor structure to form a collector region and forming a second region of a second conductivity type in the first region to form a base region. A first mask is applied including an opening defining an emitter region of the bipolar transistor. The method further includes a triple implantation process using the first mask. Thus, a third region of the first conductivity type is formed in the first region and overlaid the second region. A fourth region of the second conductivity type is formed in the second region and is more heavily doped than the second region. A fifth region of the first conductivity type is formed in the second region and above the fourth region. The fifth region forms the emitter region of the bipolar transistor.

Abstract: A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.

Abstract: A start-up circuit for voltage regulators includes a depletion mode field effect transistor (FET) having a drain electrically coupled to an input voltage, a source electrically coupled to the voltage regulator power supply input terminal and to a voltage corresponding to an output voltage of the voltage regulator, a body at a fixed voltage, and a gate electrically coupled to the output of a comparator. At start-up, the voltage regulator is powered through the FET. The drain current is self-limiting, preventing the source of the FET from rising to the level of the input voltage. When the rising output voltage of the regulator reaches a level that can operate the regulator control circuit, the comparator grounds the gate of the FET to turn off the FET, and the voltage regulator operates off of its own output. Virtually no power is dissipated in the FET during steady-state operation of the regulator.

Abstract: Each die containing a resistive element which is to be trimmed has associated therewith a plurality of alignment targets. A cut mask having a trim pattern and an alignment key formed thereon is employed in a masking and etching step to trim the resistive element to a desired resistance. The number of links cut in the resistive element, and thus the final resistance thereof, depends on the particular positioning of the cut mask with respect to the die as determined by which of the alignment targets is aligned with the alignment key. For instance, aligning the alignment key with a first alignment target would result in cutting one link in the resistive element so as to achieve a first resistance value, while re-aligning the cut mask such that the alignment key aligns with another of the alignment targets would result in cutting two links in the resistive element so as to achieve a second resistance value.

Abstract: A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to define the N-wells. The use of a single masking step to initially define the P+ isolation regions, N+ sinkers, N-wells, and P-wells results in the self-alignment of these regions. Several critical mask alignments are thereby eliminated, thus avoiding/simplifying fabrication steps, conserving die area, and allowing increased component density.

Abstract: A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.

Abstract: An improved process to fabricate a high breakdown voltage MOSFET is disclosed. The process self-aligns the channel to the source and drain and semi self-aligns the gate electrode to the channel. The MOSFET also includes a boron field implant to extend the source and drain. A high voltage gate oxide can be provided.