Abstract: A process for the preparation of an acid addition salt of an organic base comprising exposing the organic base in solid form to a gaseous acid, with the proviso that ziprasidone, its acid addition salts and intermediates thereof are excluded.

Abstract: A process for the preparation of an acid addition salt of ziprasidone base and intermediates thereof comprising exposing the ziprasidone base in solid form to a gaseous acid in a substantially dry environment.

Abstract: A process for the preparation of an acid addition salt of ziprasidone base and intermediates thereof comprising exposing the ziprasidone base in solid form to a gaseous acid in a substantially dry environment.

Abstract: A process for the preparation of an acid addition salt of an organic base comprising exposing the organic base in solid form to a gaseous acid, with the proviso that ziprasidone, its acid addition salts and intermediates thereof are excluded.

Abstract: A method and a configuration for generating a clock pulse in a data processing system having a number of independent, non-synchronous digital data channels, is described. A phase-locked loop (PLL) circuit derives a reference clock pulse, particularly from the data or a co-supplied clock pulse of a data channel serving as a reference channel, the acquired reference clock pulse is supplied to the data channels and a delay-locked loop (DLL) circuit compensates for differences in a clock pulse frequency between the reference clock pulse and the further data channels. As a result, only one reference clock pulse is sufficient in a data processing system having a number of independent, non-synchronous digital data channels, so that the jitter generated in the system is reduced.

Abstract: A method and a configuration for generating a clock pulse in a data processing system having a number of independent, non-synchronous digital data channels, is described. A phase-locked loop (PLL) circuit derives a reference clock pulse, particularly from the data or a co-supplied clock pulse of a data channel serving as a reference channel, the acquired reference clock pulse is supplied to the data channels and a delay-locked loop (DLL) circuit compensates for differences in a clock pulse frequency between the reference clock pulse and the further data channels. As a result, only one reference clock pulse is sufficient in a data processing system having a number of independent, non-synchronous digital data channels, so that the jitter generated in the system is reduced.

Abstract: A method of isolating paclitaxel from pactitaxel-containing material that includes the steps of obtaining an acetone mixture of the paclitaxel-containing material, then mixing the acetone mixture with an aqueous solvent to form an aqueous supernatant and a precipitate, wherein the precipitate contains at least 3-times higher paclitaxel content than the paclitaxel extract. The acetone/water precipitation step provides a high yield of highly pure paclitaxel that is suitable for industrial scale isolation using conventional normal-phase silica chromatography steps, and the preparation of pharmaceutical compositions containing paclitaxel.