Abstract: A Local Area Network based on a parallel bus architecture is disclosed. The LAN provides a means of utilizing relatively low cost CMOS circuitry to obtain performance superior to LAN's utilizing more exotic high speed technology. The disclosed LAN is based on a parallel bus having n×8 data lines, ± power lines, and a clock line. The bandwidth of the LAN is the product of the number of data lines times the clock speed. Bandwidth is therefore scalable by increasing either the clock speed, the number of data lines, or both. Access to the bus is provided via ports which include transceivers, a clock receiver, and a configurable hardware interface. Each port is assigned an address based on a data line and a clock cycle. The invention features a network that becomes more efficient as usage increases, ports that can accept any medium, and an architecture that facilitates implementation of a true “STAR” LAN configuration which interfaces between two or more serial communications links.

Abstract: Methods for improving bus performance and bandwidth utilization in a Local Area Network (LAN) are disclosed along with methods fo adapting LANs for use with differing hardware interfaces. The LANs described are based on a parallel bus architecture. Performance superiority is gained by passing data between ports on parallel circuits that individually are relatively slow, but that, in the aggregate, provide bandwidth equivalent to or greater than serial LAN's of much higher frequency. The bandwidth advantage of the parallel architecture is extended by the logical advantage which permits efficient utilization of up to 99% of this bandwidth. This logical advantage rests in the capability of establishing glare and collision avoidance schemes that result in very little wasted bandwidth. The LANs described are adapted for use with differing hardware interfaces when provided with a plurality of bus ports, where each port has associated therewith a configurable hardware interface.

Abstract: A Local Area Network based on a parallel bus architecture is disclosed. The LAN provides a means of utilizing relatively low cost CMOS circuitry to obtain performance superior to LAN's utilizing more exotic high speed technology. The disclosed LAN is based on a parallel bus having n×8 data lines, ±power lines, and a clock line. The bandwidth of the LAN is the product of the number of data lines times the clock speed. Bandwidth is therefore scalable by increasing either the clock speed, the number of data lines, or both. Access to the bus is provided via ports which include transceivers, a clock receiver, and a configurable hardware interface. Each port is assigned an address based on a data line and a clock cycle. The invention features a network that becomes more efficient as usage increases, ports that can accept any medium, and an architecture that facilitates implementation of a true “STAR” LAN configuration which interfaces between two or more serial communications links.

Abstract: Methods for improving bus performance and bandwidth utilization in a Local Area Network (LAN) are disclosed along with methods fo adapting LANs for use with differing hardware interfaces. The LANs described are based on a parallel bus architecture. Performance superiority is gained by passing data between ports on parallel circuits that individually are relatively slow, but that, in the aggregate, provide bandwidth equivalent to or greater than serial LAN's of much higher frequency. The bandwidth advantage of the parallel architecture is extended by the logical advantage which permits efficient utilization of up to 99% of this bandwidth. This logical advantage rests in the capability of establishing glare and collision avoidance schemes that result in very little wasted bandwidth. The LANs described are adapted for use with differing hardware interfaces when provided with a plurality of bus ports, where each port has associated therewith a configurable hardware interface.