Abstract: Disclosed in some examples is an improved computing architecture, which includes multiple processor cores and I/O devices communicating with multiple memory banks using a High Speed Interconnect Unit (HSU). The HSU quickly routes (e.g., in one clock cycle) a memory access request from an I/O device or a processor core to a particular memory bank over one of a number of independent memory routes, each memory route servicing a particular memory bank. The routing is based upon the values of preselected bit positions (“preselected bits”) in the requested memory address, the preselected bits being chosen so as to maximize the distribution of memory accesses of the entire system across all available memory banks (and by extension distributing the memory accesses across the available memory routes).

Abstract: A storage system is used for storing electrical equipment. The system includes a cabinet with storage racks vertically stacked within the cabinet. Each rack is comprised of a box having a back wall, a front wall, first and second side walls, and top and bottom walls, wherein the first and second side walls define a height of the rack. The storage racks are slidably mounted to telescoping slides rails within the cabinet. Each side wall of the rack has at least one opening. A first slide rail assembly, having a first bracket and a first slide rail, attaches the first side wall of the rack to the cabinet. A second slide rail assembly, having a second bracket and a second slide rail, attaches the second side wall of the rack to the cabinet. The brackets of the slide rail assemblies are connected to and spaced apart from the side walls and the slide rails are connected to the rack side walls. The slide rails have at least one opening substantially aligned with the openings of the rack side walls.