Abstract: A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of inserting several floating structures, namely fill structures, in a layout wiring plane, configuring the structures into structural regions, taking the regions into consideration with respect to the wiring capacities in the vicinity of these structures for a low computational outlay, and, for each structural region (3), defining a boundary polynomial that is modeled according to the outer margins of the structural region. In the calculation of the capacity coefficient, a structural region can be taken into consideration as a whole by a large filler polygon.

Abstract: With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in the layout, the capacitance with respect to other interconnection networks contained in the layout is calculated as follows: A filter polygon is determined, which corresponds to the form of the selected interconnection network, the dimensions of the filter polygon are enlarged by a predeterminable extent relative to the dimensions of the selected interconnection networks. The portions of the other interconnection networks which overlap the filter polygon are determined, and the capacitance between the selected interconnection networks and the portions of the other interconnection networks which overlap the filter polygon is determined.

Abstract: A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of inserting several floating structures, namely fill structures, in a layout wiring plane, configuring the structures into structural regions, taking the regions into consideration with respect to the wiring capacities in the vicinity of these structures for a low computational outlay, and, for each structural region (3), defining a boundary polynomial that is modeled according to the outer margins of the structural region. In the calculation of the capacity coefficient, a structural region can be taken into consideration as a whole by a large filler polygon.

Abstract: With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in the layout, the capacitance with respect to other interconnection networks contained in the layout is calculated as follows: A filter polygon is determined, which corresponds to the form of the selected interconnection network, the dimensions of the filter polygon are enlarged by a predeterminable extent relative to the dimensions of the selected interconnection networks. The portions of the other interconnection networks which overlap the filter polygon are determined, and the capacitance between the selected interconnection networks and the portions of the other interconnection networks which overlap the filter polygon is determined.