Abstract: The present disclosure provides a quantum processor realized in a semiconductor material and method to operate the quantum processor to implement adiabatic quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform adiabatic quantum error corrected computation.

Abstract: The present disclosure provides a quantum processor realized in a semiconductor material and method to operate the quantum processor to implement error corrected quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform topological quantum error corrected computation.

Abstract: The present disclosure provides a quantum processor realised in a semiconductor material and method to operate the quantum processor to implement adiabatic quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform adiabatic quantum error corrected computation.

Abstract: The present disclosure provides a quantum processor realised in a semiconductor material and method to operate the quantum processor to implement error corrected quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform topological quantum error corrected computation.

Abstract: This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves.

Abstract: This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves.