Abstract: An ion selective electrode (ISE) array is described, as well as methods for producing the same. The array can contain multiple ISE which are individually electronically addressed. The addressing allows simplified preparation of the array. The array can be used for water quality monitoring, for example.

Abstract: Gas pressure in a chamber is determined by injecting alpha particles. The alpha particles ionize the gas. By determining a number of gas ions which are ionized, the pressure of the gas in the chamber can be determined.

Abstract: An integrated charge monitor for measuring a level of cumulative radiation exposure includes semiconductor devices having characteristics that change with a cumulative level of radiation to which the devices are exposed, different amounts of radiation shielding associated with each of the devices, and circuitry operable to separately address each of the devices to measure a change in the characteristic of the selected device due to radiation exposure. The monitor may be implemented on a single integrated circuit chip. The monitor may also be employed in performing a spectrometric analysis of radiation based on the affect of the radiation on characteristics of multiple, differently-shielded semiconductor devices.

Abstract: A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.

Abstract: A p-MOSFET total dose dosimeter where the gate voltage is proportional to the incident radiation dose. It is configured in an n-WELL of a p-BODY substrate. It is operated in the saturation region which is ensured by connecting the gate to the drain. The n-well is connected to zero bias. Current flow from source to drain, rather than from peripheral leakage, is ensured by configuring the device as an edgeless MOSFET where the source completely surrounds the drain. The drain junction is the only junction not connected to zero bias. The MOSFET is connected as part of the feedback loop of an operational amplifier. The operational amplifier holds the drain current fixed at a level which minimizes temperature dependence and also fixes the drain voltage. The sensitivity to radiation is made maximum by operating the MOSFET in the OFF state during radiation soak.

Abstract: A particle sensor array which in a preferred embodiment comprises a static random access memory having a plurality of ion-sensitive memory cells, each such cell comprising at least one pull-down field effect transistor having a sensitive drain surface area (such as by bloating) and at least one pull-up field effect transistor having a source connected to an offset voltage. The sensitive drain surface area and the offset voltage are selected for memory cell upset by incident ions such as alpha-particles. The static random access memory of the present invention provides a means for selectively biasing the memory cells into the same state in which each of the sensitive drain surface areas is reverse biased and then selectively reducing the reversed bias on these sensitive drain surface areas for increasing the upset sensitivity of the cells to ions. The resulting selectively sensitive memory cells can be used in a number of applications.

Abstract: A memory system is provided, of the type which includes an error-correcting circuit that detects and corrects errors, which more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from "1" to "0" is far more likely than a switch from "0" to "1"). An asymmetric error-correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error-correcting code.

Abstract: A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the "measured length" of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor.

Abstract: A set of addressable test structures, each of which uses addressing schemes to access individual elements of the structure in a matrix, is used to test the quality of a wafer before integrated circuits produced thereon are diced, packaged and subjected to final testing. The electrical characteristic of each element is checked and compared to the electrical characteristic of all other like elements in the matrix. The effectiveness of the addressable test matrix is in readily analyzing the electrical characteristics of the test elements and in providing diagnostic information.

Abstract: Propagation delay of a signal through a channel is measured by cyclically generating a first step-wave signal for transmission through the channel to a two-input logic element and a second step-wave signal with a controlled delay to the second input terminal of the logic element. The logic element determines which signal is present first at its input terminals and stores a binary signal indicative of that determination for control of the delay of the second signal which is advanced or retarded for the next cycle until both the propagation delayed first step-wave signal and the control delayed step-wave signal are coincident. The propagation delay of the channel is then determined by measuring the time between the first and second step-wave signals out of the controlled step-wave signal generator.

Abstract: An electrical testing structure and method whereby a test structure is fabricated on, e.g., a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.