Abstract: A controller 12 has an I/O crossover switching network 14, an optional I/O network expansion 16, a plurality of serial I/O shifters 18, a clock generator 20 and I/O control logic 22. The I/O crossover-switching network 14 is also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA) 24 or an optional alternate pathway 26 which uses one of a plurality of parallel pins 28. The optional alternate pathway 26 can be used when pins 28 are unavailable or to reduce the number of pins on the device 12. The controller is shown to communicate with an external device 30 also having parallel pins 32. While a single device 30 is shown, the external device 30 can be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessor 10 of the present invention.

Abstract: An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.

Abstract: A multi-function timer used to perform multiple input timing measurements and generate multiple timed output events on the I/O pins of the apparatus. The multi-function timer comprises a plurality of slots and a compute engine. Each of the slots represents one of a plurality of timing processes. The compute engine includes a micro-sequencer and a processor. The micro-sequencer identifies a current slot and associated plurality of instructions representing a process, and is configured to serially sequence through each of the slots. The processor performs the functions of the instructions associated with each current slot. Further, each slot is configured to perform any one of the following timing processes: pulse width modulation, high speed input, high speed output, or delta time input. The multi-function timer is advantageous in that it provides application design flexibility by eliminating the need for dedicated logic for input and output timing functions.

Abstract: A controller 12 has an I/O crossover switching network 14, an optional I/O network expansion 16, a plurality of serial I/O shifters 18, a clock generator 20 and I/O control logic 22. The I/O crossover-switching network 14 is also referred to as an I/O multiplexer. Serial data may be transferred between a serial I/O shifter and an external device by way of a dedicated serial data pin (SDATA) 24 or an optional alternate pathway 26 which uses one of a plurality of parallel pins 28. The optional alternate pathway 26 can be used when pins 28 are unavailable or to reduce the number of pins on the device 12. The controller is shown to communicate with an external device 30 also having parallel pins 32. While a single device 30 is shown, the external device 30 can be any number of a plurality of devices having serial and parallel signal pathways that is controlled by the microprocessor 10 of the present invention.

Abstract: A micro-code sequencer apparatus (10) and method includes a state machine controller (14) and an instruction memory (24) for executing instructions and branches. The branch conditions for each state are stored in the state machine controller (14) whereas reprogrammable calculation instructions are stored in instruction memory (24). The instruction memory (24) is accessed by a program counter (20) which receives the decoded state information to determine the location of its instruction. A processor (30) processes the instruction and sends the output to a next state decoder (32) which determines the next state based on the branch conditions.

Abstract: A micro-sequencer apparatus (10) allows a plurality of threads to independently process one or several algorithms using common components by allowing each thread to execute one instruction during a cycle. A thread counter (12) identifies the current thread to allow processing of its instruction. A thread program counter (16) stores the program count or address for the current instruction for the current thread. An instruction memory (20) stores all instructions, and the program count identifies the particular instruction for processing. A processor (26) receives input information unique to the current thread and processes same with the current instruction to produce an output.

Abstract: A Phase Locked Loop (PLL) circuit includes a control signal generator, a digital phase detector, logic gates, a charge pump (charge/discharge circuit), a transmission gate, a loop filter, a lead-lag filter and a voltage controlled oscillator (VCO). Outputs of the digital phase detector are coupled through the logic gates to inputs of the charge pump. An output of the charge pump is coupled to the capacitor and to a first input/output of the transmission gate. A second input/output of the transmission gate is coupled to an input of the loop filter whose output is coupled to an input of the VCO whose output is coupled to a first input of the digital phase detector. A second input of the digital phase detector is coupled to a source of a reference frequency signal. The control signal generator generates non-overlapping complementary control signals with one of same connected to the logic gates and the other connected to the transmission gate.