Patents by Inventor Martin Gerhardt
Martin Gerhardt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967685Abstract: A battery module for an electric vehicle, includes a plurality of battery cells and at least one electrical resistance element arranged between the battery cells for heating the battery cells as needed. The electrical resistance element includes a polymer composition having a positive temperature coefficient.Type: GrantFiled: July 22, 2019Date of Patent: April 23, 2024Assignee: WEBASTO SEInventors: Martin Zoske, Volodymyr Ilchenko, Uwe Strecker, Nikolaus Gerhardt, Harald Bachmann, Jens Wieske
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Publication number: 20220231505Abstract: A circuit arrangement for controlling a plurality of loads of an electrical appliance has a main control module, arranged in a first voltage range and configured to generate control data for controlling a plurality of loads, which are arranged in a second voltage range. A galvanic isolation unit transfers the control data via a galvanically isolated connection from the first voltage range to the second voltage range. At least one auxiliary control module has a plurality of control outputs for the loads and an LED driver for operating a corresponding plurality of LED arrangements via the of control outputs, and/or a general-purpose input/output expansion circuit with programmable control outputs. Based on the control data, the auxiliary control module identifies a first control output for controlling the first load and causes the first load to be controlled via the first control output.Type: ApplicationFiled: January 18, 2022Publication date: July 21, 2022Inventors: Martin Gerhardt, Martin Pflauminger
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Patent number: 10580863Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.Type: GrantFiled: October 10, 2017Date of Patent: March 3, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Damien Angot, Alban Zaka, Tom Herrmann, Venkata Naga Ranjith Kuma Nelluri, Jan Hoentschel, Lars Mueller-Meskamp, Martin Gerhardt
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Patent number: 10529728Abstract: A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.Type: GrantFiled: January 30, 2018Date of Patent: January 7, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Ralf Richter, Martin Gerhardt
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Publication number: 20190109192Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.Type: ApplicationFiled: October 10, 2017Publication date: April 11, 2019Inventors: Damien Angot, Alban Zaka, Tom Herrmann, Venkata Naga Ranjith Kuma Nelluri, Jan Hoentschel, Lars Mueller-Meskamp, Martin Gerhardt
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Patent number: 10256134Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.Type: GrantFiled: June 9, 2017Date of Patent: April 9, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ricardo P. Mikalo, Martin Gerhardt
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Publication number: 20180358259Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.Type: ApplicationFiled: June 9, 2017Publication date: December 13, 2018Inventors: Ricardo P. Mikalo, Martin Gerhardt
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Publication number: 20180158833Abstract: A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.Type: ApplicationFiled: January 30, 2018Publication date: June 7, 2018Inventors: Ralf Richter, Martin Gerhardt
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Patent number: 9922986Abstract: A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.Type: GrantFiled: May 16, 2016Date of Patent: March 20, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Ralf Richter, Martin Gerhardt
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Publication number: 20170330889Abstract: A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.Type: ApplicationFiled: May 16, 2016Publication date: November 16, 2017Inventors: Ralf Richter, Martin Gerhardt
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Patent number: 9461145Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.Type: GrantFiled: October 1, 2014Date of Patent: October 4, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Ran Yan, Jan Hoentschel, Martin Gerhardt
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Patent number: 9425194Abstract: An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.Type: GrantFiled: August 6, 2015Date of Patent: August 23, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler
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Publication number: 20160099336Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.Type: ApplicationFiled: October 1, 2014Publication date: April 7, 2016Inventors: Ran YAN, Jan HOENTSCHEL, Martin GERHARDT
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Patent number: 9219013Abstract: When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated.Type: GrantFiled: March 13, 2013Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler
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Publication number: 20150340362Abstract: An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.Type: ApplicationFiled: August 6, 2015Publication date: November 26, 2015Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler
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Patent number: 9136177Abstract: Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).Type: GrantFiled: July 30, 2012Date of Patent: September 15, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler
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Patent number: 9117929Abstract: By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.Type: GrantFiled: May 16, 2011Date of Patent: August 25, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank Wirbeleit, Roman Boschke, Martin Gerhardt
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Publication number: 20140273370Abstract: When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: GLOBAL FOUNDRIES INC.Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler
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Publication number: 20140070321Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. One method includes recessing a PFET active region to form a recessed PFET surface region. A boron-doped SiGe channel is formed overlying the recessed PFET surface region.Type: ApplicationFiled: September 13, 2012Publication date: March 13, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler
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Publication number: 20140027859Abstract: Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Martin Gerhardt, Stefan Flachowsky, Matthias Kessler