Patents by Inventor Martin Giles

Martin Giles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7817861
    Abstract: A method of detecting spam images in electronic objects such as emails includes compressing images extracted from the electronic object into a common representation using a lossy compression function and determining if the compressed forms of the extracted images are identical to the compressed form of any known spam image from a corpus of known spam images, which compressed forms are the known spam images compressed into the common representation using the lossy compression function. The electronic objects are signalled as embedding a spam image on the basis of a compressed form of an extracted image extracted from an electronic object being determined to be identical to the compressed form of a known spam image.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: October 19, 2010
    Assignee: Symantec Corporation
    Inventor: Martin Giles Lee
  • Publication number: 20100025775
    Abstract: A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Inventors: Martin Giles, Titash Rakshit, Lucian Shifren, Jack Kavalieros, Willy Rachmady
  • Publication number: 20090315114
    Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
    Type: Application
    Filed: June 23, 2008
    Publication date: December 24, 2009
    Applicant: Intel Corporation
    Inventors: Titash Rakshit, Martin Giles, Ravi Pillarisetty, Jack T. Kavalieros
  • Publication number: 20090315120
    Abstract: An apparatus comprising a semiconductor substrate; a conductively doped source or drain (source/drain) region at the surface of the substrate; a raised semiconductor layer deposited over the source/drain region to form a raised source/drain region; a via formed in the raised source/drain region having substantially vertical sidewalls reaching partly or substantially to the source/drain region; and a metal contact filling the via.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Inventors: Lucian Shifren, Keith Zawadzki, Martin Giles, Cory Weber
  • Publication number: 20080299874
    Abstract: A method for restoring acid etched glass includes grinding the glass and then applying an acid resistant polyester film over the glass. Grinding may be performed in steps going from course to fine grinding pads, and stopping with a 400 grit pad, leaving a somewhat cloudy appearing surface. The polyester film fills in small irregularities in the cloudy glass surface thus eliminating the need to polish the glass.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 4, 2008
    Inventors: Timothy M. Sullivan, Martin Giles
  • Publication number: 20080209554
    Abstract: Identification of spam honeypot domains is performed automatically by a system 1. The system 1 searches sources of Internet domains based on user input to identify Internet domains which are candidates for acting as a honeypot domain. The list 7 of domains is refined by a determination unit 8 to exclude domains which are unlikely to be useful.
    Type: Application
    Filed: February 27, 2007
    Publication date: August 28, 2008
    Applicant: MessageLabs Limited
    Inventor: Martin Giles Lee
  • Publication number: 20080168144
    Abstract: A system for identifying unknown email as spam. An extractor extracts components of email which contains pseudo-random data. This data is passed to the pattern generator which identifies the pattern descriptions found within the data. Pattern descriptions which are found to match components in a store of components from previously encountered spam emails and not in a store from previously encountered non-spam emails by the pattern generator are passed to the pattern matcher. The pattern matcher examines components of unknown email extracted by the extractor. If any component from an unknown email is found to match a pattern description known to the pattern matcher, the email is identified as spam and a signal sent to the spam output, otherwise the email is identified as non-spam and a signal sent to the non-spam output.
    Type: Application
    Filed: April 4, 2006
    Publication date: July 10, 2008
    Inventor: Martin Giles Lee
  • Publication number: 20080127340
    Abstract: A method of detecting spam images in electronic objects such as emails comprises compressing images extracted from the electronic object into a common representation using a lossy compression function and determining if the compressed forms of the extracted images are identical to the compressed form of any known spam image from a corpus of known spam images, which compressed forms are the known spam images compressed into said common representation using said lossy compression function. The electronic objects are signalled as embedding a spam image on the basis of a compressed form of an extracted image extracted from an electronic object being determined to be identical to the compressed form of a known spam image.
    Type: Application
    Filed: December 11, 2006
    Publication date: May 29, 2008
    Applicant: MessageLabs Limited
    Inventor: Martin Giles Lee
  • Publication number: 20070063279
    Abstract: A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that remains substantially free of oxygen between the oxygen layer and the first surface. An annealing process is then used to diffuse nitrogen into the silicon wafer, wherein the nitrogen diffuses into the silicon device layer and the oxygen layer. Finally, a second annealing process is used to form a silicon dioxide layer and a silicon oxynitride layer, wherein the second annealing process causes the implanted oxygen to react with the silicon to form the silicon dioxide layer and causes the diffused nitrogen to migrate and react with the silicon and the implanted oxygen to form the silicon oxynitride layer.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Inventors: Peter Tolchinsky, Mohamad Shaheen, Martin Giles, Irwin Yablok, Aaron Budrevich
  • Publication number: 20060226453
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a gate structure disposed on a substrate comprising at least one recess, wherein a channel region is in a <110> direction, and then forming a compressive layer in the at least one recess.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 12, 2006
    Inventors: Everett Wang, Martin Giles, Philippe Matagne, Roza Kotlyar, Borna Obradovic, Mark Stettler
  • Publication number: 20060205167
    Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 14, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau, Everett Wang, Philippe Matagne, Lucian Shifren, Been Jin, Mark Stettler, Martin Giles
  • Publication number: 20060102988
    Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 18, 2006
    Inventors: Peter Tolchinsky, Martin Giles, Michael McSwiney, Mohamad Shaheen, Irwin Yablok
  • Publication number: 20060043579
    Abstract: A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 2, 2006
    Inventors: Jun He, Zhiyong Ma, Jose Maiz, Mark Bohr, Martin Giles, Guanghai Xu
  • Publication number: 20050167652
    Abstract: A method including forming a device on a substrate, the device including a gate electrode on a surface of the substrate; a first junction region and a second junction region in the substrate adjacent the gate electrode; and depositing a straining layer on the gate electrode.
    Type: Application
    Filed: March 1, 2005
    Publication date: August 4, 2005
    Inventors: Thomas Hoffmann, Stephen Cea, Martin Giles
  • Publication number: 20050130379
    Abstract: Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.
    Type: Application
    Filed: March 22, 2004
    Publication date: June 16, 2005
    Inventors: Mark Stettler, Borna Obradovic, Martin Giles, Rafael Rios
  • Patent number: 6872455
    Abstract: A method for enhancing the equilibrium solubility of boron ad indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: March 29, 2005
    Assignee: The Regents of the University of California
    Inventors: Babak Sadigh, Thomas J. Lenosky, Tomas Diaz de la Rubia, Martin Giles, Maria-Jose Caturla, Vidvuds Ozolins, Mark Asta, Silva Theiss, Majeed Foad, Andrew Quong
  • Publication number: 20040146722
    Abstract: A method for enhancing the equilibrium solubility of boron ad indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.
    Type: Application
    Filed: July 23, 2003
    Publication date: July 29, 2004
    Applicant: The Regents of the University of California.
    Inventors: Babak Sadigh, Thomas J. Lenosky, Tomas Diaz de la Rubia, Martin Giles, Maria-Jose Caturla, Vidvuds Ozolins, Mark Asta, Silva Theiss, Majeed Foad, Andrew Quong
  • Patent number: 6617228
    Abstract: A method for enhancing the equilibrium solubility of boron and indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: September 9, 2003
    Assignee: The Regents of the University of California
    Inventors: Babak Sadigh, Thomas J. Lenosky, Tomas Diaz de la Rubia, Martin Giles, Maria-Jose Caturla, Vidvuds Ozolins, Mark Asta, Silva Theiss, Majeed Foad, Andrew Quong
  • Publication number: 20030032268
    Abstract: A method for enhancing the equilibrium solubility of boron and indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.
    Type: Application
    Filed: September 18, 2002
    Publication date: February 13, 2003
    Applicant: The Regents of the University of California
    Inventors: Babak Sadigh, Thomas J. Lenosky, Tomas Diaz de la Rubia, Martin Giles, Maria-Jose Caturla, Vidvuds Ozolins, Mark Asta, Silva Theiss, Majeed Foad, Andrew Quong
  • Patent number: 6498078
    Abstract: A method for enhancing the equilibrium solubility of boron and indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: December 24, 2002
    Assignee: The Regents of the University of California
    Inventors: Babak Sadigh, Thomas J. Lenosky, Tomas Diaz de la Rubia, Martin Giles, Maria-Jose Caturla, Vidvuds Ozolins, Mark Asta, Silva Theiss, Majeed Foad, Andrew Quong