Abstract: The present invention provides a method for fabricating a trench capacitor having an insulation collar (10; 10a, 10b) in a substrate (1), which is electrically connected to the substrate (1) on one side via a buried contact (15a, 15b), in particular for a semiconductor memory cell having a planar select transistor which is provided in the substrate (1) and is connected via the buried contact (15a, 15b), comprising the steps of: providing a trench (5) in the substrate (1) using a hard mask (2, 3) with a corresponding mask opening; providing a capacitor dielectric (30) in the lower and middle regions of the trench, the insulation collar (10) in the middle and upper regions of the trench and an electrically conductive filling (20) at least up to the top side of the insulation collar (10); completely filling the trench (5) with a filling material (50; 50?; 50?; 20); carrying out an STI trench production process; removing the filling material (50; 50?; 50?; 20) and lowering the electrically conductive filling (20)

Abstract: In a method for producing a microelectronic electrode structure a first wiring plane is prepared, an insulating region on the first wiring plane is provided, a through-hole in the insulating region is formed, a ring electrode in the through-hole is formed, and a second wiring plane is formed on the insulating region. The ring electrode comprises a first side and a second side, the ring electrode is electrically connected on the first side to the first wiring plane, and the second wiring plane is electrically connected to the second side of the ring electrode.

Abstract: In a method for determining an edge coverage during coating processes a substrate is provided, a mask layer is deposited on the substrate, at least one through hole is formed in the mask layer and at least one first trench-type depression is formed in the substrate by patterning the substrate and the mask layer. An expanded second trench-type depression which extends in a direction parallel to the surface of the substrate is obtained by expanding isotropically the first trench-type depression. The second trench-type depression comprises a lateral trench opening at at least one lateral end region so that a coating material can penetrate laterally into the second trench-type depression through the trench opening.

Abstract: The invention relates to a method for operating a switching or amplifier device (11, 111), and to a switching or amplifier device (11, 111) comprising: an active material (13, 113) adapted to be placed in a more or less conductive state by means of appropriate switching processes; and at least three electrodes or contacts (12a, 12b, 12c).

Abstract: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

Abstract: Method for fabricating memory cells for a memory device The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench structures (105) are formed perpendicular to the surface of the driving unit (100). Deposition of a seed layer (106) on side walls (105a) of the trench structures (105) allows a crystallization agent (107) which has filled the trench structures (105), during crystallization, to have grain boundaries perpendicular to electrode surfaces that are to be formed. This provides memory cells based on vertical ferroelectric capacitors in a chain FeRAM structure.

Abstract: The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation collar (10) in the upper trench region as far as the top side of the silicon substrate (1); depositing a layer (12) made of a metal oxide in the trench (5); carrying out a thermal treatment for selectively reducing the layer (12), a region of the layer (12) that lies below the insulation collar (10) above the silicon substrate (1) being reduced and being converted into a first capacitor electrode layer (15) made of a corresponding metal silicide, and a region of the layer (12) that lies above the insulation collar (10) not being reduced; selectively removing the non-reduced region of the layer (12) that lies above the insulation collar (10); providing a capacitor dielectric layer (18) in the trench (5) above the first capacitor electrode layer (15); and providing a second capaci

Abstract: The present invention provides a process for producing a gate element for a transistor, in which a substrate (101) is provided, an insulation layer (104) and a sacrificial layer (105) are deposited on the substrate (101), the sacrificial layer (105) is patterned and a spacing layer (107) is deposited on the sacrificial layer, the spaces in the patterned sacrificial layer (105) are filled with a filling layer (108), the sacrificial layer structure (105a, 105b) and regions of the insulation layer (104) which are located beneath the sacrificial layer structure (105a, 105b) are removed. Finally, recesses (110) are etched into the substrate (101), the spacing layer (107) and those regions of the insulation layer which are not covered by the filling layer (108) are removed, a gate oxide layer (111) of the gate element is deposited and a gate electrode layer (112) of the gate element is deposited in the recesses (110).

Abstract: The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate (1; 1?, 60, 1?) having a front side (VS) and a rear side (RS); providing trenches (5) in the semiconductor substrate (1; 1?, 60, 1?) proceeding from the front side (VS) of the semiconductor substrate (1; 1?, 60, 1?); providing a respective inner capacitor electrode (6) in the trenches (5); uncovering the inner capacitor electrodes (6) proceeding from the rear side (RS) of the semiconductor substrate (1; 1?, 60, 1?); providing a capacitor dielectric (40) on the uncovered inner capacitor electrodes (6); and providing outer capacitor electrodes (50) on the capacitor dielectric (40) on the inner capacitor electrodes (6).

Abstract: In order to fabricate a semiconductor memory, a trench capacitor is arranged in a first trench. Beside the first trench, a first longitudinal trench and, parallel on the other side of the first trench, a second longitudinal trench are arranged in the substrate. A first spacer word line is arranged in the first longitudinal trench and a second spacer word line is arranged in the second longitudinal trench. There are arranged in the first trench connecting webs between the first spacer word line and the second spacer word line which have a thickness which, in the direction of the first spacer word line, is less than half the width of the first trench in the direction of the first spacer word line.

Abstract: The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive element (100), the substrate (101) provided as an electrode layer is conditioned, a dielectric layer (102) is deposited on the conditioned substrate (101) and a second electrode layer (104) is applied on the layer stack produced, the layer stack being modified by a heat treatment in such a way that the dielectric layer (102) deposited on the conditioned substrate (101) forms a dielectric mixed layer (105) with a reaction layer (103) deposited on the dielectric layer (102), which dielectric mixed layer has an increased dielectric constant (k) or an increased thermal stability.

Abstract: The present invention provides a method for fabricating a stacked capacitor array (1), which comprises a regular arrangement of a plurality of stacked capacitors (2), with a stacked capacitor (2) being at a shorter distance from the respective adjacent stacked capacitor (2) in certain first directions (3) than in certain second directions (4), comprising the following method steps: provision of an auxiliary layer stack (5) having first auxiliary layers (6) with a predetermined etching rate and at least one second auxiliary layer (7) with a higher etching rate on a substrate (8); etching of in each case one hollow cylinder (9) for each stacked capacitor (2) through the auxiliary layer stack (5) in accordance with the regular arrangement, with the auxiliary layer stack (5) being left in place in intermediate regions (10) between the hollow cylinders (9); isotropic etching of the second auxiliary layers (7) to form widened portions (11) of the hollow cylinders (9), without any second auxiliary layer (7) being le

Abstract: The present invention relates to a stacked capacitor array and a fabrication method for a stacked capacitor array having a multiplicity of stacked capacitors, an insulator keeping at least two adjacent stacked capacitors mutually spaced apart, so that no electrical contact can arise between them and the stacked capacitors are mechanically stabilized.

Abstract: In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.

Abstract: A method is taught for fabricating patterned silicon dioxide layers on process areas disposed perpendicularly or at an inclination to a substrate surface. Firstly, a starter layer having leaving groups is produced by non-conformal deposition of a reactive component. Tris(tert-butoxy)silanol is subsequently added. The addition of the tris(tert-butoxy)silanol leads to the formation of a silicon dioxide layer selectively only on the starter layer.

Abstract: The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate (101), which forms a first electrode, a trench-like recess (102) etched into the substrate (101), conductive material, which is provided as a projection in a central region of the trench-like recess (102) and spaced apart from the side walls (107) of the trench-like recess (102) and is in electrical contact with the substrate at the base (104) of the trench-like recess (102), a dielectric layer (108), which has been deposited on the side walls (107) of the trench-like recess (102), the base (104) of the trench-like recess (102) and the surfaces of the conductive material (105), and an electrode layer (110), which has been deposited on the dielectric layer (108) and forms a second electrode.

Abstract: An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being deposited one on top of another and in each case being conditioned after they have been deposited. In this way, the internal stress of the electrode layer can be reduced, and therefore a breaking strength and a resistance to leakage currents of the trench capacitor can be increased.

Abstract: A method for producing memory cells, in which an electrically conductive substrate is provided, a trench structure or cup structure with side walls and a base is formed in or on the substrate, a first insulation layer is deposited at the side walls, a capacitor material is deposited on the base, a nanostructure is grown starting from and electrically connected to the catalyst material deposited on the base, a second insulation layer is deposited on the nanostructure and on the base, and finally an electrically conductive layer is deposited as a counterelectrode on the first insulation layer and second insulation layer.

Abstract: Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.

Abstract: A method for fabricating a trench capacitor in a semiconductor substrate with a low-impedance inner electrode for use in memory cells of memory devices. A separating layer is provided on a dielectric layer in the active region of the trench capacitor. Afterward, a low-impedance inner electrode made of metal or a metal compound is introduced both in the active region and in the collar region lined with an insulation layer.