Abstract: A method of determining the bit error ratio (BER) of a device under test (DUT) includes transmitting a first signal of an original test bit pattern over a first channel to a receiver of the DUT, and forward error correction (FEC) encoding the original test bit pattern of the first signal transmitted to the receiver of the DUT in a loopback mode of the DUT to generate an FEC encoded test bit pattern. The method further includes transmitting a second signal of the FEC encoded test bit pattern from a transmitter of the DUT over a second channel, and FEC decoding the FEC encoded test bit pattern of the second signal to obtain a decoded test bit pattern and comparing the decoded test bit pattern with the original test bit pattern to determine a BER of the DUT.

Abstract: A method of determining the bit error ratio (BER) of a device under test (DUT) includes transmitting a first signal of an original test bit pattern over a first channel to a receiver of the DUT, and forward error correction (FEC) encoding the original test bit pattern of the first signal transmitted to the receiver of the DUT in a loopback mode of the DUT to generate an FEC encoded test bit pattern. The method further includes transmitting a second signal of the FEC encoded test bit pattern from a transmitter of the DUT over a second channel, and FEC decoding the FEC encoded test bit pattern of the second signal to obtain a decoded test bit pattern and comparing the decoded test bit pattern with the original test bit pattern to determine a BER of the DUT.

Abstract: An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit (40) is coupled to the level comparator (30) for sampling (SAM) the comparator output signal (COS). A bit error test unit (60) receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

Abstract: An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit (40) is coupled to the level comparator (30) for sampling (SAM) the comparator output signal (COS). A bit error test unit (60) receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

Abstract: For identifying or localizing a serial data stream in a deserialized output provided at a plurality of n output ports (PORT1-PORT5), a pattern recognition is provided at each one of the plurality of n output ports (PORT1-PORT5) for recognizing a deserialized identifier pattern corresponding to an identifier pattern within the serial data stream and for detecting a phase of the deserialized identifier pattern in the deserialized output. The phase of the output of each respective port (PORT1-PORT5) is then shifted in correspondence with the detected phase of the deserialized identifier pattern.

Abstract: For identifying or localizing a serial data stream in a deserialized output provided at a plurality of n output ports (PORT1-PORT5), a pattern recognition is provided at each one of the plurality of n output ports (PORT1-PORT5) for recognizing a deserialized identifier pattern corresponding to an identifier pattern within the serial data stream and for detecting a phase of the deserialized identifier pattern in the deserialized output. The phase of the output of each respective port (PORT1-PORT5) is then shifted in correspondence with the detected phase of the deserialized identifier pattern.