Abstract: A semiconductor circuit arrangement is disclosed. In one embodiment, a semiconductor module is attached to a board using a screw, with a mechanical and electrical contact being made between module contacts on the semiconductor module and associated board contacts on the board at the same time by attachment using the screw.

Abstract: A power semiconductor module has a ceramic substrate (9) which has on at least one side a patterned metallization (50) with a fineness of pattern of smaller than or equal to 800 ?m, a first semiconductor chip (10) which has a power semiconductor component and which is arranged on the patterned metallization (50), and a second semiconductor chip (30) which has drive electronics for driving the first semiconductor chip (10) and which is arranged on the patterned metallization (50). Furthermore, at least one thin-wire bond (2, 3) with a bonding-wire diameter (d2, d3) of smaller than or equal to 75 ?m is provided which is formed between the patterned metallization (50) and the second semiconductor chip (30).

Abstract: A semiconductor circuit arrangement is disclosed. In one embodiment, a semiconductor module is attached to a board using a screw, with a mechanical and electrical contact being made between module contacts on the semiconductor module and associated board contacts on the board at the same time by attachment using the screw.

Abstract: A power semiconductor module has a ceramic substrate (9) which has on at least one side a patterned metallization (50) with a fineness of pattern of smaller than or equal to 800 ?m, a first semiconductor chip (10) which has a power semiconductor component and which is arranged on the patterned metallization (50), and a second semiconductor chip (30) which has drive electronics for driving the first semiconductor chip (10) and which is arranged on the patterned metallization (50). Furthermore, at least one thin-wire bond (2, 3) with a bonding-wire diameter (d2, d3) of smaller than or equal to 75 ?m is provided which is formed between the patterned metallization (50) and the second semiconductor chip (30).

Abstract: In order to obtain a minimal leakage inductance in a semiconductor component, it is necessary to provide at least two adjacent switching elements whose load current connection elements which are adjacent on one housing side to have different polarities. A multiplicity of even-numbered switching elements are advantageously disposed next to one another on an alignment line. The leads between the load current connection elements and the load current connections of the switching elements that are disposed next to one another advantageously run approximately orthogonally with respect to the alignment line. The assigned load current connection elements then alternately have the first and the second supply potential and this minimizes the leakage inductance.

Abstract: In order to obtain a minimal leakage inductance in a semiconductor component, it is necessary to provide at least two adjacent switching elements whose load current connection elements which are adjacent on one housing side to have different polarities. A multiplicity of even-numbered switching elements are advantageously disposed next to one another on an alignment line. The leads between the load current connection elements and the load current connections of the switching elements that are disposed next to one another advantageously run approximately orthogonally with respect to the alignment line. The assigned load current connection elements then alternately have the first and the second supply potential and this minimizes the leakage inductance.