Abstract: A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.

Abstract: The present invention provides a process for obtaining solid recovered fuel and synthesis gas from a waste-based feedstock, comprising the steps of: I. converting the feedstock into a solid recovered fuel by means of a number of parameters pertaining to waste sorting, selection, comminution and/or screening; II. gasifying under suitable reaction conditions at least a portion of the solid recovered fuel to produce synthesis gas and by-product(s); and III. optionally cleaning at least a portion of the synthesis gas to produce clean synthesis gas and wastewater, wherein one or more of the solid recovered fuel, synthesis gas, and by-product(s) of the gasification are analysed during operation of the process, and wherein data from said analysis is used to control one or more parameters of step I) in order to influence reaction conditions in step II, and optionally step III).

Abstract: The present invention provides a process for obtaining solid recovered fuel and synthesis gas from a waste-based feedstock, comprising the steps of: I. converting the feedstock into a solid recovered fuel by means of a number of parameters pertaining to waste sorting, selection, comminution and/or screening; II. gasifying under suitable reaction conditions at least a portion of the solid recovered fuel to produce synthesis gas and by-product(s); and III. optionally cleaning at least a portion of the synthesis gas to produce clean synthesis gas and wastewater, wherein one or more of the solid recovered fuel, synthesis gas, and by-product(s) of the gasification are analysed during operation of the process, and wherein data from said analysis is used to control one or more parameters of step I) in order to influence reaction conditions in step II, and optionally step III).

Abstract: A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four “slots,” each including four bytes, and locates scalar data in “preferred slots” to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: Image analysis apparatus has a cathode ray tube and an associated light pen. The light pen can be used to draw on the screen of the cathode ray tube a frame around a feature. A detector connected to receive the video signals only responds to features within that frame. The apparatus can be switched to another mode in which the cathode ray tube displays, to a higher magnification, a point indicated on the screen of the cathode ray tube using the light pen.

Abstract: An image analyser for use in a line-by-line scanning system in which a field of an article is scanned to produce a video signal representative instantaneously of a point within that field. The analyser has n delay means connected in series where n is an integer divisible by 2, the video signal being applied to the input of the first delay means. The input of the first delay means and the output of each delay means other than the nth/2 delay means in the series, are connected to the inputs of an adder. The output of the nth/2 delay means in the series is connected to the input of a signal multiplier circuit. The outputs of the adder and of the multiplier are connected to a subtracting circuit which produces an output representative of the output of the multiplier minus the output of the adder.