Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

Abstract: In a preferred embodiment, a diffused leakage resistor of a high value between approximately 200K ohms and 5M ohm is formed proximate to an MOS power transistor on the same silicon chip. The manufacturer of the chip has the option, using a mask, to connect or not connect the dedicated leakage resistor between the transistor's source and gate during the fabrication of the chip. The resistor is formed using the same masking steps already used to form the MOS transistor. To increase the sheet resistivity (ohms per square) of the resistor, a novel method is used to cause the effective width of the diffused resistor to be substantially narrower than the actual drawn width dimension on the mask. Also using this novel method, the concentration and depth of the dopants forming the resistor diffused region are less than that of the source and drain regions. The resulting resistor will thus have a much higher sheet resistivity than is achieved using conventional methods.

Abstract: A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.

Abstract: A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

Abstract: One embodiment of the invention includes multiple patterns on a single mask, where all the patterns on the single mask are used for forming a single product. In the preferred embodiment, each of four quadrants of a mask have a different process layer pattern, where each of the four patterns is associated with a different process layer for the same product. After exposure of the wafer using the mask, the mask is rotated 90.degree. for the next exposure step so that the mask pattern image for the next layer to be formed on the wafer will overlie the designated quadrant of the wafer which will contain the final product. Although, by using this technique, three-quarters of the wafer will be unusable, this partial waste of the wafer will be offset by the savings in mask costs with low volume production, in prototyping situations, and in product debugging. Using the above technique, conventional mask exposure machines may be used.

Abstract: In a preferred embodiment, a diffused leakage resistor of a high value between approximately 200K ohms and 5M ohm is formed proximate to an MOS power transistor on the same silicon chip. The manufacturer of the chip has the option, using a mask, to connect or not connect the dedicated leakage resistor between the transistor's source and gate during the fabrication of the chip. The resistor is formed using the same masking steps already used to form the MOS transistor. To increase the sheet resistivity (ohms per square) of the resistor, a novel method is used to cause the effective width of the diffused resistor to be substantially narrower than the actual drawn width dimension on the mask. Also using this novel method, the concentration and depth of the dopants forming the resistor diffused region are less than that of the source and drain regions. The resulting resistor will thus have a much higher sheet resistivity than is achieved using conventional methods.

Abstract: A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

Abstract: In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for the PNP transistor is self-aligned with the base region of the NPN transistor. All the defined regions are then doped to achieve a desired base region concentration. A next masking step forms a layer of resist over the base region, and the remainder of the previous masking pattern is retained to define the emitter and collector regions of the PNP transistor. P-type dopants are then implanted in the previously defined emitter and collector regions to form the heavily doped P++ emitter and collector regions of the PNP transistor. Thus, the P++ emitter and collector regions of the PNP transistor will be self-aligned with the P-type base region of the NPN transistor.

Abstract: A polysilicon or equivalent plate, to be used as an upper plate of the capacitor, is first formed over an oxide layer grown on a substrate. The length of the upper plate is made shorter than gate lengths of MOS transistors formed with the same process so that, after dopants are deposited into exposed regions of the substrate on both sides of the plate in a manner identical to forming self-aligned source and drain regions of an MOS transistor, the dopants will side-diffuse during drive-in and the diffused regions will be closely separated or merged under the plate. The resulting capacitor structure has a more stable capacitance with varying V.sub.GS levels than MOS transistors merely connected and used as capacitors and has a lower series resistance.

Abstract: A method is disclosed for forming a shorting contact for shorting P-type and N-type conductivity regions in a semiconductor together. In one embodiment of this method, the P-type region is substantially a square and is surrounded by the N-type region. A substantially square contact opening is made to expose the P-type region and a portion of the N-type region. Sides of the contact opening are formed to be at substantially 45 degree angles with respect to sides of the substantially square P-type region. In this manner, the alignment tolerance for forming the contact opening is less critical than if the sides of the contact opening were parallel to the sides of the P-type region. The contact opening is then filled with a conductive material to electrically short the P-type region to the N-type region. The conductivity types in this example may be reversed.

Abstract: In one embodiment of the invention, a P diffused region, acting as an anode of a zener diode, is formed within an N+ sinker which is part of a vertical transistor in a configurable integrated circuit. This N+ sinker contacts an N+ buried layer or an N+ substrate and provides an exposed contact region for the transistor. Conductivity types may, of course, be opposite to those described in this embodiment. In this way, an additional zener diode is made available to a user without requiring additional die area. Additionally, since the zener diode is not formed from emitter and base regions of a bipolar transistor, the breakdown voltage of the zener diode may be set as desired. By forming a P zener diode anode in all N+ sinkers, or, conversely, forming a N zener cathode in all P+ sinkers, a large number of zener diodes may be made available to a user without adding any die area to the configurable integrated circuit.

Abstract: A diamond-shaped short contact overlapping two differing conductivity regions in a semiconductor. The shape and orientation providing maximum alignment tolerances for a given size of contact opening.

Abstract: A multilayer polysilicon structure is formed, where the various polysilicon layers and a conductive diffused region form plates of stacked capacitors, and electrodes contact each of the capacitor plates. The resulting capacitor structure inherently forms a series connected capacitor structure where each capacitor shares a plate with an adjacent capacitor. The structure is well suited for use in a voltage multiplier where each capacitor is charged to the supply voltage with the total voltage across the series connected capacitors being a multiple of the supply voltage. The dielectric layer between each of the polysilicon layers and between the first polysilicon layer and the diffused region may be nitride, oxide, or a combination of both.

Abstract: In an oxide isolated semiconductor structure having an epitaxial layer formed on a monocrystalline substrate, a buried, laterally extending, PN junction in said structure, and oxidized isolation regions extending through said epitaxial layer to said PN junction, thereby to form a plurality of electrically isolated pockets of semiconductor material, a dopant is located in those regions of the semiconductor material directly adjacent the oxidized isolation regions. This dopant is often referred to as the field predeposition.The processes which result in the subsequent formation of insulating material to create isolated epitaxial pockets also result in the formation of a conductive buried region resulting from that portion of the field predeposition between the epitaxial pockets and portions of the wall of the insulating material. If desired, a collector sink then may be formed in the epitaxial pocket without disrupting the function of the conductive buried region.