Abstract: A compensation circuit is configured to compensate for a loss of low-frequency signal content of an input signal at a receiver input. The compensation circuit includes a switching circuit and a summing circuit coupled to the switching circuit. The switching circuit is configured to receive a first plurality of digitized values sampled from a receiver output signal. The summing circuit is configured to generate a summation signal based on a combination of a first plurality of input values selected by the switching circuit. The selecting is based on the first plurality of digitized values. The compensation circuit is configured to provide to the receiver input a compensation signal to compensate for the loss of the low-frequency signal content from the input signal. The compensation signal is based on the summation signal and is a function of at least one gain value.

Abstract: A compensation circuit is configured to compensate for a loss of low-frequency signal content of an input signal at a receiver input. The compensation circuit includes a switching circuit and a summing circuit coupled to the switching circuit. The switching circuit is configured to receive a first plurality of digitized values sampled from a receiver output signal. The summing circuit is configured to generate a summation signal based on a combination of a first plurality of input values selected by the switching circuit. The selecting is based on the first plurality of digitized values. The compensation circuit is configured to provide to the receiver input a compensation signal to compensate for the loss of the low-frequency signal content from the input signal. The compensation signal is based on the summation signal and is a function of at least one gain value.

Abstract: An integrated circuit (300/400) includes first and second power domains and a bank of input/output (I/O) cells (305/405) coupled to the first and second power domains. The bank of I/O cells (305/405) includes a first plurality of active clamps (374/445) for the first power domain and a second plurality of active clamps (384/425) for the second power domain wherein the first (374/445) and second (384/425) pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element (425, 445) for a respective second power domain. According to another aspect, each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.

Abstract: A low-pass filter circuit is disposed on a monolithic integrated circuit. An operational amplifier receives a reference potential and drives three parallel stacked diode paths into a current supply. One of the stacked diode paths conducts the vast majority of the current allowing the transistors of the other two stacked diode paths to operate in a sub-threshold region and represent an extremely high resistance. The high resistances in combination with a low value capacitor realizes a low-pass filter on the monolithic integrated circuit.