Abstract: A field effect transistor (FET) structure suitable for MOS and CMOS IC fabrication processes includes spaced apart alternating source and drain regions distributed in a rectangular checkerboard pattern of horizontal and vertical rows. A first grid of intersecting horizontal and vertical conductive gate lines overlaps adjacent source and drain regions of the array and is dielectrically isolated from the source and drain regions by an insulating layer. The horizontal and vertical gate lines provide a single gate element distributed across the array which reduces FET channel length and channel resistance. A second grid comprising a set of parallel diagonal alternating source lead lines and drain lead lines is dielectrically isolated from the first grid. The source lead lines are electrically coupled to source regions and drain lead lines to drain regions.