Patents by Inventor Martin J. Gasper
Martin J. Gasper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8779820Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.Type: GrantFiled: November 25, 2013Date of Patent: July 15, 2014Assignee: LSI CorporationInventors: Martin J. Gasper, Michael J. McManus
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Publication number: 20140082577Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.Type: ApplicationFiled: November 25, 2013Publication date: March 20, 2014Applicant: LSI CorporationInventors: Martin J. Gasper, Michael J. McManus
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Patent number: 8664995Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.Type: GrantFiled: August 8, 2013Date of Patent: March 4, 2014Assignee: LSI CorporationInventors: Martin J. Gasper, Michael J. McManus
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Publication number: 20130321054Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.Type: ApplicationFiled: August 8, 2013Publication date: December 5, 2013Applicant: LSI CorporationInventors: Martin J. Gasper, Michael J. McManus
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Patent number: 8536921Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.Type: GrantFiled: March 23, 2012Date of Patent: September 17, 2013Assignee: LSI CorporationInventors: Martin J. Gasper, Michael J. McManus
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Patent number: 8461893Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages.Type: GrantFiled: August 16, 2011Date of Patent: June 11, 2013Assignee: LSI CorporationInventors: Martin J. Gasper, Gerard M. Blair, Bruce E. Zahn
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Publication number: 20130069703Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.Type: ApplicationFiled: March 23, 2012Publication date: March 21, 2013Inventors: Martin J. Gasper, Michael J. McManus
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Publication number: 20130043923Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values. The delay stage includes M parallel-coupled inverter stages. Each parallel-coupled inverter stage includes N pairs of stacked PMOS transistors and stacked NMOS transistors. The N transistor pairs have configurable source-drain node connections between a drain node and a source node of each transistor in the pair, wherein the selectable delay value corresponds to a configuration of the configurable source-drain node connections to adjust a delay value of each of the M inverter stages.Type: ApplicationFiled: August 16, 2011Publication date: February 21, 2013Inventors: Martin J. Gasper, Gerard M. Blair, Bruce E. Zahn
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Patent number: 7712066Abstract: A power switching circuit is provided for use in an integrated circuit including at least a first voltage rail and a second voltage rail. The power switching circuit includes at least one MOS device having a first source/drain adapted for connection to the first voltage rail, a second source/drain adapted for connection to the second voltage rail, and a gate adapted for receiving a control signal. The MOS device selectively connects the first voltage rail to the second voltage rail in response to the control signal. The first and second voltage rails form a grid overlying the power switching circuit, the first and second voltage rails being formed in different planes relative to one another. The connection between the power switching circuit and the first voltage rail is made at an interface between the first and voltage rails.Type: GrantFiled: December 29, 2005Date of Patent: May 4, 2010Assignee: Agere Systems, Inc.Inventors: Martin J. Gasper, Jr., James C. Parker, Clayton E. Schneider, Jr.
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Patent number: 7590961Abstract: An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal in the digital circuitry of the integrated circuit to a desired amount. The digital logic cell and the skew adjusting cell are selected from a cell library.Type: GrantFiled: July 6, 2007Date of Patent: September 15, 2009Assignee: Agere Systems Inc.Inventors: Martin J. Gasper, Jr., Bernard L. Morris
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Patent number: 4203389Abstract: An apparatus is disclosed herein which automatically regulates the amount of oxygen in a body of water by sensing the oxygen content of the water and activating a spray aerator whenever the percentage of oxygen falls below a predetermined value.Type: GrantFiled: October 13, 1978Date of Patent: May 20, 1980Assignee: Rodale Resources, Inc.Inventors: Martin J. Gasper, Jr., Theodore W. Black