Abstract: A device and method for clock and data recovery are disclosed. For example, an integrated circuit comprises a first branch for recovering a clock signal from an input signal. The first branch includes a phase and frequency detector for detecting a phase and a frequency of the clock signal and a numerically controlled oscillator that is controlled by the phase and the frequency of the clock signal from the phase and frequency detector. The integrated circuit also includes a second branch for recovering a data signal from the input signal. The second branch includes a pre-settable numerically controlled oscillator that is pre-settable with the phase and the frequency of the clock signal from the numerically controlled oscillator. The second branch also includes a sample selector that is controlled by the pre-settable numerically controlled oscillator for recovering the data signal.

Abstract: A method is provided for preparing a plurality of systems that include respective programmable integrated circuits (ICs) of the same type. A plurality of circuit designs is partitioned into a base design and respective supplemental designs. The base design includes a set of input/output pins utilized by any of the plurality of circuit designs. A supplemental bitstream is generated for each of the supplemental designs. A first bitstream is generated for implementing the base circuit design, a communication module, and a reconfiguration module in a first portion of programmable resources of the programmable IC. The reconfiguration module is configured to program, in response to each respective one of the supplemental bitstreams received via the communication module, a second portion of the programmable resources with the supplemental bitstream to implement a corresponding one of the plurality of circuit designs.