Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer. The TFT may be a top gate TFT wherein the thin film sublayer is formed on the semiconductor channel layer, and wherein the printed sublayer is formed over the thin film sublayer. Alternatively, the TFT may be a bottom gate TFT wherein the printed sublayer is formed over the gate electrode; wherein the thin film sublayer is formed over the printed sublayer, and wherein the semiconductor channel layer is formed on the thin film sublayer.

Abstract: A method of forming a thin film transistor comprises providing first electrode layers (42) over a transparent substrate (40), the first electrode layers comprising a lower transparent layer (42a), and an upper opaque layer (42b). The first electrode layers are patterned to define a first electrode pattern in which an edge region of the transparent layer (42a) extends beyond an edge region of the opaque layer (42b). A transistor body region comprising a semiconductor layer (16) defining the channel area of the transistor and a gate insulator layer (18) is provided over the first electrode pattern (42). A transparent second electrode layer (46) is also provided. A negative resist (70) is exposed through the substrate (40), with regions of the negative resist layer (70) shadowed by the opaque layer (42b) of the first electrode pattern (42) remaining unexposed.

Abstract: A method of manufacturing an active matrix device (10) comprising a row and column array of active elements wherein each element comprises a transparent pixel electrode (12) associated with a self-aligned, top gate transistor (14, R2) having a transparent gate electrode (26). The method comprising the steps of forming opaque source (22) and drain (22′) electrodes on a transparent substrate (51); forming a semiconductor channel layer (23) so as to join source (22) and drain (22′) electrodes; forming a gate insulating (24, 25) layer; and depositing a transparent conductive layer and forming both the transparent gate electrode (26) and the pixel electrode (32) therefrom.

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer.

Abstract: A method of forming a thin film transistor comprises providing first electrode layers (42) over a transparent substrate (40), the first electrode layers comprising a lower transparent layer (42a), and an upper opaque layer (42b). The first electrode layers are patterned to define a first electrode pattern in which an edge region of the transparent layer (42a) extends beyond an edge region of the opaque layer (42b). A transistor body region comprising a semiconductor layer (16) defining the channel area of the transistor and a gate insulator layer (18) is provided over the first electrode pattern (42). A transparent second electrode layer (46) is also provided. A negative resist (70) is exposed through the substrate (40), with regions of the negative resist layer (70) shadowed by the opaque layer (42b) of the first electrode pattern (42) remaining unexposed.

Abstract: A method of forming a thin film transistor comprises providing first electrode layers (42) over a transparent substrate (40), the first electrode layers comprising a lower transparent layer (42a), and an upper opaque layer (42b). The first electrode layers are patterned to define a first electrode pattern in which an edge region of the transparent layer (42a) extends beyond an edge region of the opaque layer (42b). A transistor body region comprising a semiconductor layer (16) defining the channel area of the transistor and a gate insulator layer (18) is provided over the first electrode pattern (42). A transparent second electrode layer (46) is also provided. A negative resist (70) is exposed through the substrate (40), with regions of the negative resist layer (70) shadowed by the opaque layer (42b) of the first electrode pattern (42) remaining unexposed.

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer. The TFT may be a top gate TFT wherein the thin film sublayer is formed on the semiconductor channel layer, and wherein the printed sublayer is formed over the thin film sublayer. Alternatively, the TFT may be a bottom gate TFT wherein the printed sublayer is formed over the gate electrode; wherein the thin film sublayer is formed over the printed sublayer, and wherein the semiconductor channel layer is formed on the thin film sublayer.

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer.

Abstract: An X-ray examination apparatus comprises an X-ray source, an X-ray detector (3) and an X-ray filter arranged between the X-ray source and the X-ray detector. The X-ray filter comprises a plurality of filter elements each comprising a vessel containing an X-ray absorbing liquid, the liquid level in each vessel determining the X-ray absorptivity of the respective filter element. Control means is provided for applying electric voltages to the individual filter elements to change the liquid levels within an adjust time period. The control means is arranged to apply a respective control voltage to each individual filter element a repeat number of times within the adjust time period, the repeat number being selected so as substantially to maximize the rate of change of liquid level of the filter elements. This enables patient examination times to be reduced, by reducing the times between sequential images.

Abstract: A method of manufacturing an active matrix device (10) comprising a row and column array of active elements wherein each element comprises a transparent pixel electrode (12) associated with a self-aligned, top gate transistor (14, R2) having a transparent gate electrode (26). The method comprising the steps of forming opaque source (22) and drain (22′) electrodes on a transparent substrate (51); forming a semiconductor channel layer (23) so as to join source (22) and drain (22′) electrodes; forming a gate insulating (24, 25) layer; and depositing a transparent conductive layer and forming both the transparent gate electrode (26) and the pixel electrode (32) therefrom.

Abstract: An ion implantation process comprises performing mass separation of ions from an ionised source of phosphorus so as to select the P2 ions and reject phosphorus hydride ion species. The P2 ions are injected into a semiconductor substrate. The rejection of phosphorus hydride ions species is facilitated because there are no such species adjacent (in terms of effective mass) the P2 ion species. The use of the P2 ion species also improves the implantation process for shallow implantation depths.

Abstract: A thin film transistor has source (20) and drain (10) electrodes which each comprise a coiled elongate portion. One (14) of these portions coils inwardly to a central connector portion (12), and the other (22) coils outwardly to a peripheral connector portion (16). The two coiled portions are interlinked to define between them a substantially uniform spacing (24) corresponding to a channel region of the transistor. This arrangement enables the length to width ratio of the transistor to be reduced, giving rise to an increased current capacity of the transistor. By making one elongate portion (14) longer than the other (22), the transistor can have a source-gate capacitance lower than its drain-gate capacitance. These transistors may form switching elements in large area electronic devices, such as electroluminescent displays, plasma displays, electrostatic print heads, and X-ray dynamic beam attenuators.

Abstract: An image sensor comprises switching elements 30 on a substrate 1. An insulating separation layer 9 is disposed over the switching elements so that a photodiode arrangement 20a disposed over the insulating separation layer 9, can overlap the switching elements 30 and occupy a maximum area of the image sensor. A barrier layer 10 is interposed between the insulating separation layer 9 and the photodiode arrangement 20a, which prevents degradation of the photodiode characteristics over time.

Abstract: In the manufacture of a flat panel display or other large-area electronics device, a self-aligned thin-film transistor (TFT) is formed with source and drain silicide parts (31,32) adjacent an insulated gate structure (25,21,22) on a silicon film (20) which provides a transistor body (20a) comprising a channel area (20b) of the transistor. The transistor has its source and drain electrode pattern (11,12) extending under the silicon film (20). The insulated gate structure (25,21,22) is formed as a conductive gate (25) on an insulating film (21,22) which is patterned together with the conductive gate (25). A silicide-forming metal (30) is deposited over the insulated gate structure (25,21,22) and over exposed, adjacent areas (20c and 20d) of the silicon film, and the metal is reacted to form the silicide (31,32) with these adjacent areas of the silicon film.

Abstract: An image detector (1, 1a) has an array (2) of sensors (3) formed from layers of material provided on a substrate (4) and separated from a biasing electrode (5) by a radiation conversion layer (6) in which charge carriers are generated in response to incident radiation. Each sensor has a collecting electrode (7a, 7b) for collecting charge carriers generated in the radiation conversion layer (6), a capacitor (c) for storing charge and a switching element (8) having at least first and second electrodes (9 and 10) with one (10) of the first and second electrodes being coupled to the collecting electrode (7a, 7b) for enabling charge carriers stored at the sensor (3) to be read out.

Abstract: A large area active matrix array (2) is manufactured by providing four substrates (1) each carrying a sub-array (21) having an active area (11) comprising a matrix of switching elements (30) and associated row and column conductors (41) and (42) for enabling addressing of individual switching elements (30). The row and column conductors (41) and (42) terminate in respective connecting leads (41a and 42a) extending beyond the active area (11). A portion (1a) of each substrate (1) and the connecting leads carried is removed so as to form a new substrate edge (1'a) adjacent each of two adjoining edges of the active area (11) and the substrates (1) are mounted onto a support (12) so that each new substrate edge is adjacent another new substrate edge (1'a) to form the large area array (2), thereby allowing the same pixel pitch to be maintained across the array (2). Each sub-array (2') may be fully tested before completion of the array (2) which should allow higher yields.