Patents by Inventor Martin Jay Kinkade

Martin Jay Kinkade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200395064
    Abstract: Various implementations described herein are related to a device having a memory cell with logic that is configured to store data and passgates that are configured to access the data stored in the logic. The device may include a first number of input-output ports that are time-multiplexed with the passgates so as to increase the first number of input-output ports to a second number of input-output ports that is greater than the first number of input-output ports.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 17, 2020
    Inventors: Yew Keong Chong, Bikas Maiti, Venu Anantuni, Martin Jay Kinkade
  • Patent number: 10839934
    Abstract: Various implementations described herein refer to an integrated circuit. The integrated circuit may include memory circuitry having multiple bitcell arrays with redundant rows of bitcells. The integrated circuit may include comparator logic disposed outside the memory circuitry to de-assert access to one or more faulty rows of bitcells and to assert access to the redundant rows of bitcells.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 17, 2020
    Assignee: Arm Limited
    Inventors: Rahul Mathur, Andy Wangkun Chen, Gaurang Prabhakar Narvekar, Sanjay Mangal, Yew Keong Chong, Bikas Maiti, Martin Jay Kinkade
  • Publication number: 20190371424
    Abstract: Various implementations described herein refer to an integrated circuit. The integrated circuit may include memory circuitry having multiple bitcell arrays with redundant rows of bitcells. The integrated circuit may include comparator logic disposed outside the memory circuitry to de-assert access to one or more faulty rows of bitcells and to assert access to the redundant rows of bitcells.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Inventors: Rahul Mathur, Andy Wangkun Chen, Gaurang Prabhakar Narvekar, Sanjay Mangal, Yew Keong Chong, Bikas Maiti, Martin Jay Kinkade
  • Patent number: 9620200
    Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.
    Type: Grant
    Filed: March 26, 2016
    Date of Patent: April 11, 2017
    Assignee: ARM Limited
    Inventors: Sanjay Mangal, Gus Yeung, Martin Jay Kinkade, Rahul Mathur, Bal S. Sandhu, George McNeil Lattimore
  • Patent number: 9070431
    Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: June 30, 2015
    Assignee: ARM Limited
    Inventors: Frank Guo, Martin Jay Kinkade, Bo Zheng, Brian Reed, Shrisagar Dwivedi
  • Patent number: 9064559
    Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 23, 2015
    Assignee: ARM Limited
    Inventors: Bikas Maiti, Yew Keong Chong, Martin Jay Kinkade
  • Publication number: 20150117119
    Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.
    Type: Application
    Filed: October 25, 2013
    Publication date: April 30, 2015
    Applicant: ARM LIMITED
    Inventors: Frank GUO, Martin Jay Kinkade, Bo Zheng, Brian Reed, Shrisagar Dwivedi
  • Publication number: 20150049563
    Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: ARM LIMITED
    Inventors: Bikas MAITI, Yew Keong CHONG, Martin Jay KINKADE
  • Publication number: 20140115554
    Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.
    Type: Application
    Filed: December 31, 2013
    Publication date: April 24, 2014
    Applicant: ARM LIMITED
    Inventors: Gus YEUNG, Martin Jay KINKADE, Marlin Wayne FREDERICK, JR.
  • Patent number: 8645893
    Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 4, 2014
    Assignee: ARM Limited
    Inventors: Gus Yeung, Martin Jay Kinkade, Marlin Wayne Frederick, Jr.
  • Patent number: 8611172
    Abstract: A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: December 17, 2013
    Assignee: ARM Limited
    Inventors: Amaranth Shyanmugam, Bikas Maiti, Vincent Phillipe Schuppe, Yew Keong Chong, Martin Jay Kinkade, Hsin-Yu Chen
  • Publication number: 20130308407
    Abstract: A semiconductor memory storage device having a plurality of storage cells for storing data, each storage cell comprising an access control device and access control circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line to: control the voltage control switching circuitry to connect the at least one capacitor to the voltage supply line such that the at least one capacitor is charged by the voltage supply line and a voltage level on the voltage supply line is reduced; and to control the access control line switching circuitry to connect the selected access control line to the voltage supply line having the reduced voltage level.
    Type: Application
    Filed: May 21, 2012
    Publication date: November 21, 2013
    Applicant: ARM LIMITED
    Inventors: Amaranth Shyanmugam, Bikas Maiti, Vincent Philippe Schuppe, Yew Keong Chong, Martin Jay Kinkade, Hsin-Yu Chen
  • Patent number: 8358551
    Abstract: A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: January 22, 2013
    Assignee: ARM Limited
    Inventors: Jacek Wiatrowski, Martin Jay Kinkade, Yew Keong Chong
  • Patent number: 8218391
    Abstract: An integrated circuit memory 10, 12 has clock control circuitry 36 responsive to a clock signal CLK and a chip enable signal CEN to generate control signals for controlling the integrated circuit memory 10 in response to the clock signal CLK when the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is active. When the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is disabled, then power control circuitry 38 serve to switch portions of the integrated circuit memory 10, 12, such as word line driver circuitry 24, sense amplifiers 22 and buffer circuitry 30, into a low power state from an operating state. When the chip enable signal CEN activates the integrated circuit memory 10, 12, the power control circuitry 38 switches these portions 24, 22, 30 which are in the low power state back to the operating state.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 10, 2012
    Assignee: ARM Limited
    Inventors: Martin Jay Kinkade, Gus Yeung, Yew Keong Chong
  • Publication number: 20120002499
    Abstract: An integrated circuit memory 10, 12 has clock control circuitry 36 responsive to a clock signal CLK and a chip enable signal CEN to generate control signals for controlling the integrated circuit memory 10 in response to the clock signal CLK when the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is active. When the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is disabled, then power control circuitry 38 serve to switch portions of the integrated circuit memory 10, 12, such as word line driver circuitry 24, sense amplifiers 22 and buffer circuitry 30, into a low power state from an operating state. When the chip enable signal CEN activates the integrated circuit memory 10, 12, the power control circuitry 38 switches these portions 24, 22, 30 which are in the low power state back to the operating state.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 5, 2012
    Inventors: Martin Jay Kinkade, Gus Yeung, Yew Keong Chong
  • Publication number: 20110158021
    Abstract: A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 30, 2011
    Applicant: ARM LIMITED
    Inventors: Jacek Wiatrowski, Martin Jay Kinkade, Yew Keong Chong
  • Patent number: 7650524
    Abstract: The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal, at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one latch in response to a predetermined clock signal value; clock signal distribution means operable to distribute said clock signal to said plurality of latches and said at least one tristateable device; wherein in response to a sleep signal said circuit is operable to: reduce a voltage difference across at least a portion of said circuit such that said portion of said circuit is powered down; and maintain a voltage difference across at least one stora
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: January 19, 2010
    Assignee: ARM Limited
    Inventors: Marlin Frederick, Jr., Martin Jay Kinkade
  • Patent number: 7606108
    Abstract: A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 20, 2009
    Assignee: ARM Limited
    Inventors: David Anthony New, Gus Yeung, Martin Jay Kinkade, David John Willingham
  • Publication number: 20090129194
    Abstract: A multiport memory 2 is provided with control circuitry 14 which detects signal values indicative of concurrent write and read accesses via respective bit lines of a plurality of data access ports to a common row of bit cells. When such signals are detected, an override signal is generated and supplied to override circuitry 34, 36, 38, 40, 42, 44. The override circuitry is responsive to the override signal to drive one or more bit values being written to respective bit cells via their associated bit lines onto associated bit lines of other of a plurality of data access supports that are concurrently enabled for access to their bit cells. Thus, write data is also written onto the bit lines associated with a port performing a concurrent read operation.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 21, 2009
    Applicant: ARM LIMITED
    Inventors: David Anthony New, Gus Yeung, Martin Jay Kinkade, David John Willingham
  • Patent number: 7221205
    Abstract: A clocked scan flip-flop 2 is provided in which a latch 14 within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch 14 via a sleep mode path 20 through a transmission gate 22 (or other tristate driver) controlled by a sleep mode control signal SLP. The diagnostic clock signal SCLK, the operational clock signal CLK and the sleep mode control signal SLP together provide the control operations for controlling the various elements within the clocked-scan flip-flop 2 to move into and out of sleep mode.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: May 22, 2007
    Assignee: Arm Limited
    Inventors: Martin Jay Kinkade, Marlin Frederick