Patents by Inventor Martin Jeffrey Ambrose

Martin Jeffrey Ambrose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Peripheral component interconnect (PCI) backplane connectivity system on chip (SoC)
    Patent number: 11880333
    Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: January 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Jason A. T. Jones, Sriramakrishnan Govindarajan, Mihir Narendra Mody, Kishon Vijay Abraham Israel Vijayponraj, Bradley Douglas Cobb, Sanand Prasad, Gregory Raymond Shurtz, Martin Jeffrey Ambrose, Jayant Thakur
  • PERIPHERAL COMPONENT INTERCONNECT (PCI) BACKPLANE CONNECTIVITY SYSTEM ON CHIP (SoC)
    Publication number: 20210263883
    Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Inventors: Jason A.T. Jones, Sriramakrishnan Govindarajan, Mihir Narendra Mody, Kishon Vijay Abraham Israel Vijayponraj, Bradley Douglas Cobb, Sanand Prasad, Gregory Raymond Shurtz, Martin Jeffrey Ambrose, Jayant Thakur
  • Peripheral component interconnect (PCI) backplane connectivity system on chip (SoC)
    Patent number: 11030144
    Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 8, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jason A. T. Jones, Sriramakrishnan Govindarajan, Mihir Narendra Mody, Kishon Vijay Abraham Israel Vijayponraj, Bradley Douglas Cobb, Sanand Prasad, Gregory Raymond Shurtz, Martin Jeffrey Ambrose, Jayant Thakur
  • PERIPHERAL COMPONENT INTERCONNECT (PCI) BACKPLANE CONNECTIVITY SYSTEM ON CHIP (SoC)
    Publication number: 20200192859
    Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Jason A.T. JONES, Sriramakrishnan GOVINDARAJAN, Mihir Narendra MODY, Kishon Vijay Abraham ISRAEL VIJAYPONRAJ, Bradley Douglas COBB, Sanand PRASAD, Gregory Raymond SHURTZ, Martin Jeffrey AMBROSE, Jayant THAKUR
  • Real-time scheduling method with reduced input/output latency and improved tolerance for variable processing time
    Patent number: 9240189
    Abstract: A method and apparatus for processing encoded audio data that operates on batches of data having a predetermined time block size. An input/output memory buffer provides a delay from input to corresponding output of 2+x time blocks where x is a predetermined constant and 0<x<1.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Martin Jeffrey Ambrose, Lester Anderson Longley
  • Real-Time Scheduling Method with Reduced Input/Output Latency and Improved Tolerance for Variable Processing Time
    Publication number: 20140257823
    Abstract: A method and apparatus for processing encoded audio data that operates on batches of data having a predetermined time block size. An input/output memory buffer provides a delay from input to corresponding output of 2+x time blocks where x is a predetermined constant and 0<x<1.
    Type: Application
    Filed: January 8, 2014
    Publication date: September 11, 2014
    Inventors: Martin Jeffrey Ambrose, Lester Anderson Longley