Abstract: An image sensor may be formed from stacked first and second substrates. An array of imaging pixels and verification circuitry may be formed in the first substrate. Row control circuitry may be formed in the second substrate. The row control circuitry may provide row control signals to the array of imaging pixels. The verification circuitry may also receive the row control signals from the row control circuitry. The first substrate may include a plurality of n-channel metal-oxide semiconductor transistors and may not include any p-channel metal-oxide semiconductor transistors. The verification circuitry may include an SR latch circuit with an S node coupled to a pull-up line and an R node coupled to a pull-down transistor to ensure the SR latch circuit starts up in a set state. The verification circuitry may include a level shifter that shifts a control signal voltage when the control signal is at a low level.

Abstract: An image sensor may be formed from stacked first and second substrates. An array of imaging pixels and verification circuitry may be formed in the first substrate. Row control circuitry may be formed in the second substrate. The row control circuitry may provide row control signals to the array of imaging pixels. The verification circuitry may also receive the row control signals from the row control circuitry. The first substrate may include a plurality of n-channel metal-oxide semiconductor transistors and may not include any p-channel metal-oxide semiconductor transistors. The verification circuitry may include an SR latch circuit with an S node coupled to a pull-up line and an R node coupled to a pull-down transistor to ensure the SR latch circuit starts up in a set state. The verification circuitry may include a level shifter that shifts a control signal voltage when the control signal is at a low level.