Abstract: A bi-directional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2. If the voltage on one of the nodes, IO1 or IO2, rises with a fast input edge rate, tending to cause the gate voltage V1 to go too high due to capacitive coupling (source-gate or drain-gate), node N1 is coupled through an appropriate capacitor, C1 or C2, to another node N3, which is normally held low by a transistor MN9. The voltage on N3 drives the gate of a transistor MN10, connected to node N1, to pull the gate voltage V1 of MN1 low, tending to discharge the capacitive coupling due to the overlap capacitance of MN1, which tends to turn MN1 OFF and also allows the voltage V1 to decay very quickly, so as to prevent some of the charge from IO1 getting through to IO2.

Abstract: A bidirectional control circuit for preventing the improper functioning of a pass transistor MN1 in a CMOS circuit due to abnormally high voltages on its source and drain nodes IO1 and IO2. If the voltage on one of the nodes, IO1 or IO2, rises with a fast input edge rate, tending to cause the gate voltage V1 to go too high due to capacitive coupling (source-gate or drain-gate), node N1 is coupled through an appropriate capacitor, C1 or C2, to another node N3, which is normally held low by a transistor MN9. The voltage on N3 drives the gate of a transistor MN10, connected to node N1, to pull the gate voltage V1 of MN1 low, tending to discharge the capacitive coupling due to the overlap capacitance of MN1, which tends to turn MN1 OFF and also allows the voltage V1 to decay very quickly, so as to prevent some of the charge from IO1 getting through to IO2.