Patents by Inventor Martin K. Kinyua

Martin K. Kinyua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Switched-capacitor circuits with reduced finite-gain effect
    Patent number: 7126415
    Abstract: Operational amplifier circuits (20, 30) including error capacitors (C3, C13) for storing finite gain effect error voltages for correction of output voltages of the circuits (20, 30), are disclosed. The circuits (20, 30) are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (15, 25), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter (50) using the disclosed operational amplifier circuits (20, 30) is also disclosed.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: October 24, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Franco Maloberti, Martin K. Kinyua
  • Switched-capacitor circuits with reduced finite-gain effect
    Patent number: 7068203
    Abstract: Operational amplifier circuits (20, 30) including error capacitors (C3, C13) for storing finite gain effect error voltages for correction of output voltages of the circuits (20, 30), are disclosed. The circuits (20, 30) are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (15, 25), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter (50) using the disclosed operational amplifier circuits (20, 30) is also disclosed.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Franco Maloberti, Martin K. Kinyua
  • Switched-capacitor circuits with reduced finite-gain effect
    Publication number: 20060071709
    Abstract: Operational amplifier circuits (20, 30) including error capacitors (C3, C13) for storing finite gain effect error voltages for correction of output voltages of the circuits (20, 30), are disclosed. The circuits (20, 30) are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (15, 25), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter (50) using the disclosed operational amplifier circuits (20, 30) is also disclosed.
    Type: Application
    Filed: November 23, 2005
    Publication date: April 6, 2006
    Inventors: Franco Maloberti, Martin K. Kinyua