Patents by Inventor Martin Käs

Martin Käs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11633492
    Abstract: The compound of formula (II) is an advantageous intermediate for improving the process of synthesizing the linker-drug vc-seco-DUBA, as well as for the overall process for preparing an antibody-drug conjugate comprising the vc-seco-DUBA linker-drug. The methods of making the compound of formula (II) can include recovery of the compound as a solid, such as via crystallization, in high yields and purity.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: April 25, 2023
    Assignee: Byondis B.V.
    Inventors: Vladimir Janousek, Martin Kas
  • Patent number: 11434243
    Abstract: The invention relates to an improved process for preparing triazoloquinazolinones of Formula (I), including 9-benzyl-2-(4-methylphenyl)-2,6-dihydro[1,2,4]triazolo[4,3-c]quinazoline-3,5-dione, pharmaceutical compositions comprising the compounds of Formula (I), including 9-benzyl-2-(4-methylphenyl)-2,6-dihydro[1,2,4]triazolo[4,3-c]quinazoline-3,5-dione, prepared by the improved process, and methods of treatment using the compounds of Formula (I), including 9-benzyl-2-(4-methylphenyl)-2,6-dihydro[1,2,4]triazolo[4,3-c]quinazoline-3,5-dione, prepared by the improved process.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 6, 2022
    Assignee: GABATHER AB
    Inventors: Thomas Jagusch, Peter Adrianus Hubertus Zenhorst, Paula Anna Adriana Van Der Aa, Govert Arie Verspui, Martin Kas, Martina Scigelova
  • Patent number: 8809121
    Abstract: A method of dividing a two dimensional array of encapsulated integrated circuits into individual integrated circuit packages uses a first series of parallel cuts (32) extending fully through the leadframe (16) and encapsulation layer (14), and defining rows of the array. The cuts terminate before the beginning and end of the rows such that the integrity of the array is maintained by edge portions (34) at the ends of the rows. After plating contact pads (18), a second series of parallel cuts (36) is made extending fully through the leadframe (16) and encapsulation layer (14). This separates the array into columns thereby providing singulation of packages between the edge portions (34).
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: August 19, 2014
    Assignee: NXP B.V.
    Inventors: Martin Ka Shing Li, Max Leung, Pompeo Umali
  • Publication number: 20130302945
    Abstract: A method of dividing a two dimensional array of encapsulated integrated circuits into individual integrated circuit packages uses a first series of parallel cuts (32) extending fully through the leadframe (16) and encapsulation layer (14), and defining rows of the array. The cuts terminate before the beginning and end of the rows such that the integrity of the array is maintained by edge portions (34) at the ends of the rows. After plating contact pads (18), a second series of parallel cuts (36) is made extending fully through the leadframe (16) and encapsulation layer (14). This separates the array into columns thereby providing singulation of packages between the edge portions (34).
    Type: Application
    Filed: September 29, 2010
    Publication date: November 14, 2013
    Applicant: NXP B.V.
    Inventors: Martin Ka Shing Li, Max Leung, Pompeo Umali
  • Patent number: 8263176
    Abstract: A method for fabricating a photovoltaic element with stabilized efficiency is proposed. The method comprises the following steps: preparing a boron-doped, oxygen-containing silicon substrate; forming an emitter layer on a surface of the silicon substrate; and a stabilization treatment step. The stabilization treatment step comprises keeping the temperature of the substrate during a treatment time within a selectable temperature range having a lower temperature limit of 50° C., preferably 90° C., more preferably 130° C. and even more preferably 160° C. and an upper temperature limit of 230° C., preferably 210° C., more preferably 190° C. and even more preferably 180° C., and generating excess minority carriers in the silicon substrate during the treatment time, for example, by illuminating the substrate or by applying an external voltage. This method can be used to fabricate a photovoltaic element, e.g.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: September 11, 2012
    Assignee: Universität Konstanz
    Inventors: Axel Herguth, Gunnar Schubert, Martin Käs, Giso Hahn, Ihor Melnyk
  • Publication number: 20110162716
    Abstract: A method and device for fabricating a photovoltaic element with stabilized efficiency is proposed. The method comprises the following steps: preparing a boron-doped, oxygen-containing silicon substrate; forming an emitter layer on a surface of the silicon substrate; and a stabilization treatment step. The stabilization treatment step comprises keeping the temperature of the substrate during a treatment time within a selectable temperature range having a lower temperature limit of 50° C., preferably 90° C., more preferably 130° C. and even more preferably 160° C. and an upper temperature limit of 230° C., preferably 210° C., more preferably 190° C. and even more preferably 180° C., and generating excess minority carriers in the silicon substrate during the treatment time, for example, by illuminating the substrate or by applying an external voltage. This method can be used to fabricate a photovoltaic element, e.g.
    Type: Application
    Filed: December 17, 2010
    Publication date: July 7, 2011
    Applicant: Universitat Konstanz
    Inventors: Axel Herguth, Gunnar Schubert, Giso Hahn, Ihor Melnyk, Martin Käs
  • Publication number: 20100243036
    Abstract: A method for fabricating a photovoltaic element with stabilised efficiency is proposed. The method comprises the following steps: preparing a boron-doped, oxygen-containing silicon substrate; forming an emitter layer on a surface of the silicon substrate; and a stabilisation treatment step. The stabilisation treatment step comprises keeping the temperature of the substrate during a treatment time within a selectable temperature range having a lower temperature limit of 50° C., preferably 90° C., more preferably 130° C. and even more preferably 160° C. and an upper temperature limit of 230° C., preferably 210° C., more preferably 190° C. and even more preferably 180° C., and generating excess minority carriers in the silicon substrate during the treatment time, for example, by illuminating the substrate or by applying an external voltage. This method can be used to fabricate a photovoltaic element, e.g.
    Type: Application
    Filed: March 21, 2007
    Publication date: September 30, 2010
    Applicant: Universitat Konstanz
    Inventors: Axel Herguth, Gunnar Schubert, Martin Käs, Giso Hahn, Ihor Melnyk
  • Publication number: 20100130746
    Abstract: Processes for making zoledronic acid can be advantageously carried out in a solvent/diluent that comprises a mixture of (i) a polyalkylene glycol and (ii) a cyclic carbonate of the formula (3) wherein n is an integer from 2 to 4, and R1 and R2 each independently represent a hydrogen or a C1-C4 alkyl group.
    Type: Application
    Filed: November 27, 2009
    Publication date: May 27, 2010
    Inventors: Martin Kas, Michal Benes, Jaroslav Pis
  • Patent number: D774066
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: December 13, 2016
    Assignee: TD Ameritrade IP Company, Inc.
    Inventors: Martin Kas, Rahul Mahesh Kulkarni
  • Patent number: D812085
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 6, 2018
    Assignee: TD Ameritrade IP Company, Inc.
    Inventors: Martin Kas, Rahul Mahesh Kulkarni
  • Patent number: D812086
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 6, 2018
    Assignee: TD Ameritrade IP Company, Inc.
    Inventor: Martin Kas
  • Patent number: D812637
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 13, 2018
    Assignee: TD Ameritrade IP Company, Inc.
    Inventor: Martin Kas
  • Patent number: D816694
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 1, 2018
    Assignee: TD Ameritrade IP Company, Inc.
    Inventors: Martin Kas, Rahul Mahesh Kulkarni