Abstract: System and method of correcting etch and lithographic processes on a photo mask provides for performing an etch proximity correction on a layout design pattern. A first and a second intermediate layout pattern each being based on the etch proximity corrected layout design pattern are provided. An optical proximity correction on the first intermediate layout pattern is performed so as to generate a modified first intermediate layout pattern. Scatterbar generation on the second intermediate layout pattern is performed so as to generate a modified second intermediate layout pattern including scatterbars. Generating a mask layout pattern being based on the first and the second modified intermediate layout pattern is performed.

Abstract: A respectively separate optical proximity correction (OPC) process model and method is formed for selected structure classes or partial patterns of a layout is disclosed. For this purpose, the corresponding structure elements are treated separately as early as during the modeling. During the modeling and also for OPC correction, the structure elements in the layout to be corrected are selected in correspondingly rule-based fashion. The thus selected elements of the layout are simulated and corrected with the separately formed OPC process models. The errors in the description of the imaging process are smaller for the separate OPC process models than for a uniform OPC process model, which has the effect of improving the accuracy of the imaging on the wafer in subsequent layout transfer processes.

Abstract: In order to compensate for the shortening of line ends (30) in a circuit design of an integrated circuit, in a first step, hammerheads or serifs (50) are attached to the line ends (30) by means of rule-based OPC corrections. The line ends modified in this way are revised further by downstream application of a simulation-based OPC correction before mask or direct wafer writer data are calculated. As a result of the formation of the pattern revised by the simulation-based correction on the wafer, there actually arises in an approximate manner owing to the proximity effects the layout created by the rule-based correction with the supplemented line ends (30) on the wafer.