Abstract: A method for preparing an NMR material, comprising generating parahydrogen in gas or liquid form at a first location; transporting the parahydrogen away from the first location; mixing a precursor compound including a metabolite component with a catalyst for hydrogenation; hydrogenating the precursor compound using the parahydrogen; transferring polarization in the precursor compound to a nuclear spin of the metabolite component; cleaving a side arm of the precursor compound in a chemical reaction, with the metabolite molecule being one of the products of the reaction; separating the metabolite molecule from the catalyst for hydrogenation and other products of the reaction; and generating metabolite molecules for use in an MRI scanner by extracting a sample of the metabolite molecule having at least 5% polarization.

Abstract: This application discloses a memory built-in self-test system to prompt a memory device to sense values of stored data using a reference trim during memory read operations. The memory built-in self-test system can automatically set the reference trim for the memory device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the memory device to perform the memory read operations with different test values for the reference trim. The memory built-in self-test system also includes a trim feedback circuit to determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data.

Abstract: A memory device can sense stored data during memory read operations using a reference trim, and a memory built-in self-test system can perform a multiple step process to set the reference trim for the memory device. The memory built-in self-test system can set a reference trim range that corresponds to a range of available reference trim values and then select one of the reference trim values in the reference trim range as the reference trim for the memory device. The memory built-in self-test system can set the reference trim range by prompting performance of the memory read operations using different positions of the reference trim range relative to read characteristics of the memory device and set a position for the reference trim range relative to the read characteristics of the memory device based on failures of the memory device to correctly sense the stored data during the memory read operations.

Abstract: A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.

Abstract: A reconfigurable scan network in a circuit is configured such that a first scan path is used if a programmable component has no stuck-at fault and a second scan path is used if the programmable component has a stuck-at fault. A test pattern having a length equal to a length of the second path is shifted into the reconfigurable scan network, and a part or a whole of the test pattern is then shifted out from the reconfigurable scan network. The part or the whole of the test pattern being shifted out is analyzed to determine whether the programmable component has the stuck-at fault.

Abstract: Aspects of the invention relate to test access architecture for stacked memory and logic dies. A test access interface for a logic die that is stacked under a memory die is disclosed. The disclosed test access interface can control testing logic core, interconnections with the memory die and with another logic die. The controlling of testing interconnections with the memory die is through a memory boundary scan register controller in the test access interface.

Abstract: Aspects of the invention relate to test access architecture for stacked dies. The disclosed test access interface for a die can function as a stand-alone test access interface, allowing both pre-bond testing and post-bond testing of the die. In a stack of dies, the test access interface of a die may be enabled/disabled by the test access interface of an adjacent die.

Abstract: Aspects of the invention relate to test access architecture for stacked dies. The disclosed test access interface for a die can function as a stand-alone test access interface, allowing both pre-bond testing and post-bond testing of the die. In a stack of dies, the test access interface of a die may be enabled/disabled by the test access interface of an adjacent die.

Abstract: Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern.

Abstract: Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported.

Abstract: Methods, apparatus, and systems for computing and analyzing integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the described methods are also disclosed.

Abstract: A device and method for detecting a delay time of a circuit is provided. A test signal is fed into the circuit, the test signal including a signal edge, the occurrence of which is related to a reference time. The output signal of the circuit is sampled at predetermined times to obtain a sequence of sample values, with a first state being associated with a sample value when the output signal has a first signal value and a second state being associated with a sample value when the output signal has a second signal value. A counter counts the sample values of the sequence, to which an equal state is associated, to obtain counted sample values. A delay time is calculated using the counted number of sample values.

Abstract: Methods, apparatus, and systems for computing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary method disclosed herein, information is received from processing test responses of integrated circuits designed for functional use in electronic devices. In this embodiment, the information is indicative of integrated circuit failures observed during testing of the integrated circuits and of possible yield limiting factors causing the integrated circuit failures. Probabilities that one or more of the possible yield limiting factors in the integrated circuits actually caused the integrated circuit failures are determined by statistically analyzing the received information. The probabilities that one or more possible yield limiting factors actually caused the integrated circuit failures are reported.

Abstract: Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, one or more fault dictionaries are generated for identifying one or more defect candidates from corresponding observation point combinations. In this exemplary method, the observation point combinations indicate the observation points of a circuit-under-test that captured faulty test values upon application of a respective test pattern.

Abstract: Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, design defect extraction rules are derived at least partially from a set of design manufacturing rules. Potential defects are extracted from a representation of an integrated circuit layout using the design defect extraction rules. Circuit test stimuli applied during one or more circuit tests are determined. Test responses resulting from the applied circuit tests are evaluated to identify integrated circuits that fail and to identify the occurrence in the failing integrated circuits of one or more potential types of defects associated with the applied circuit tests.

Abstract: The device for detecting a delay time of a circuit includes a feeder for feeding a test signal into the circuit, the test signal comprising a signal edge the occurrence of which is related to a reference time; a sampler for sampling an output signal of the circuit at predetermined times to obtain a sequence of sample values, a first state being associated to a sample value when the output signal has a first signal value and a second state being associated to a sample value when the output signal has a second signal value; a counter for counting the sample values of the sequence, to which an equal state is associated, starting from the reference time or another reference time, the time interval of which to the reference time being known to obtain a counted number of sample values; and a calculator for calculating the delay time using the counted number of sample values and the reference time.

Abstract: In a method and an apparatus for monitoring a selected group of fuel cells of a high-temperature fuel cell stack, a change over time in an averaged electrical voltage of the fuel cells of the selected group is ascertained and compared with a reference value that detects at least a change over time in a voltage of other fuel cells. The method permits a reliable detection of the failure of one fuel cell of a stack with simple measures.

Abstract: A method is provided for operating a PEM fuel cell plant containing at least one PEM fuel cell block and a speed-controlled compressor upstream of the PEM fuel cell block for supplying air at a volume flow rate. The speed of the compressor is controlled to a desired value for adjusting the electric current of the PEM fuel cell block to a given value. The desired value is derived from the given value of the electric current. This measure ensures a simple control of the air volume flow rate for the PEM fuel cell block with low apparatus requirements. A PEM fuel cell plant is also provided.

Abstract: A process for operating a PEM fuel cell unit containing at least one PEM fuel cell block and a speed-controlled compressor connected upstream. To control changing an electrical current I of the PEM fuel cell block to a new reference value I.sub.SN, a speed n of the compressor is set in a first step to a maximum value n.sub.M and in a second step is reduced to a speed n.sub.SN corresponding to the new reference value I.sub.SN. By this expedient improved dynamics for brief and rapid load changes are achieved.