Abstract: A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links configured for full duplex, synchronized communication. A node is configured to communicate a mailbox message with one or more connected nodes, the mailbox message having a flexible message size or flexible destination defined based on register access. A node includes a mailbox register configured to store a message header and one or more words of a current message for one or both of a transmit direction or a receive direction. The node includes a message buffer configured to store one or more messages including the current message for transmission or reception. The node includes a tunnel controller configured to communicate the current message from or to the message buffer as one or more mailbox packets with one or more of the connected nodes that participate in a mailbox tunnel over the daisy-chain.

Abstract: A log splitter includes a chassis having a support table configured to support a log to be split, a splitter screw having a generally conical shape and mounted to a rotatable screw shaft that is supported by the chassis, and a drive assembly configured to rotate the shaft to impart rotational movement to the splitter screw about a screw axis. The drive assembly includes a motor coupled to the screw shaft via a constant velocity transmission (CVT) (also known as continuously variable transmission). The CVT can provide both high speed and high torque during the splitting process as required to split the log. A fall restriction bar helps restrict a person from accidentally falling onto the splitter screw. An engine-kill bar is pivotally mounted to the chassis. A log-rotation stop mechanism is configured to restrict rotation of a log that gets stuck on the splitter screw.

Abstract: A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links. The plurality of nodes are configured for full-duplex, synchronized communication over the bus links for transmission of Ethernet frames within a flexible payload of superframes on the bus links. A node is configured to: determine that the node has a transmit token; transmit an Ethernet frame within a tunnel on the full-duplex bus links in at least one of an upstream direction towards a main-node or a downstream direction towards an end-sub-node; receive, while transmitting the Ethernet frame, a request for the transmit token from one or more other nodes in the tunnel on at least one of the full-duplex bus links in a direction opposite the Ethernet frame; and transmit the transmit token to a next node based on an order of priority of the one or more other nodes.

Abstract: A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links, wherein the plurality of nodes are configured for full duplex, synchronized communication via a carrier-based modulation scheme over the bus links. A node is configured to: transmit a downstream synchronization control header (DnSCH) to a downstream node; receive an upstream synchronization response header (UpSRH) from the downstream node; measure a delay between the DnSCH and the UpSRH; send delay information to the downstream node in a DnSCH; receive a time adjusted UpSRH; and communicate with the downstream node and any upstream node over frames based on the delay information. The frames may include a header; a flexible payload defined by a stream mapping that assigns a byte location within the flexible payload to a stream; and a footer.

Abstract: Disclosed herein are systems and techniques for remote bus enable. In some embodiments, a communication system with remote enable functionality may include: a master transceiver coupled to a downstream link of a bus; a voltage regulator, wherein the voltage regulator has a voltage output and an enable input, and the voltage output is coupled to the master transceiver; and a switch coupled to the enable input of the voltage regulator.

Abstract: Aspects of the present disclosure include methods and systems for transmitting digital information including generating digital information, converting the digital information to two or more transmission signals, outputting each of the two or more transmission signals onto a respective wire of two wires of a cable for at least a first slave node, and outputting a supply current via the two wires for at least the first slave node.

Abstract: The invention relates to a conductor assembly (1), in particular for use in electric vehicles or hybrid vehicles, comprising at least one planar first current-conducting component (10) having a first outer face (12) and a first inner face (13) facing away from the first outer face (12), and comprising at least one planar second current-conducting component (20) having a second outer face (22) and a second inner face (23) facing away from the second outer face (22), wherein the second current-conducting component (20) is arranged in such a way that the second inner face (23) of the second current-conducting component (20) is opposite the first inner face (13) of the first current-conducting component (10).

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: In some examples of both networks and methods, a data communication network includes a plurality of nodes. The nodes include a main node (MN) and at least one sub node (SNi=SN0, . . . SNX). Each node includes a node transceiver. The node transceiver is operable to perform data communication in accordance with a first network protocol for power over data via a pair of conductors (e.g., the conductors of bus). A physical layer includes a cable segment (e.g., the cable segment of bus) between each node. Each cable segment includes a plurality of pairs of conductors (e.g., pairs) and a connector (e.g., 8P8C connector—though other connectors with multiple pairs of conductors can be used) at each end. A first pair of the conductors (e.g., connected to pin 4 and pin 5 of the 8P8C connector) implements the first network protocol between the nodes. One or more of the remaining pairs of the conductors provide supplemental power to the nodes 102.

Abstract: A network includes nodes. The nodes include a main node (MN) and a plurality of sub nodes (SNi=SN0, . . . SNX). Each node includes a node transceiver that is operable to perform data communication in accordance with a first network protocol. Each node transceiver includes and a positive power contact (V+) and a negative power contact (V?) operable to power the node transceiver to perform the data communication. The data communication network includes a two conductor combined power and data physical layer/medium. The physical layer connects the SN0 V+ to a bus power source positive power contact (VS+) in a first conductive path. The physical layer connects the MN V? and SNX V? to the bus power source negative power contact (VS?) in a second conductive path. The physical layer connects each SNi V?, for i=0 to X?1, to the SNi+1 V+ in the first conductive path.

Abstract: Disclosed herein are systems and techniques for microphone array calibration, as well as communication systems in which calibrated microphones can be used. The systems and techniques disclosed herein may provide both phase and magnitude calibration for microphone arrays, resulting in improved performance for beamforming and other applications. Further, various systems and methods are disclosed herein for local storage of calibration coefficients in the microphone array (e.g., at the time of manufacture and calibration). Further, various systems and methods disclosed herein may include central application of the calibration of a microphone array (e.g., in an edge processor at operation time) to replace uncalibrated microphone signals with calibrated microphone signals further down in the signal chain.

Abstract: Disclosed herein are systems and techniques for node discovery and configuration in a daisy-chained network. For example, in some embodiments, a main node may “auto-discover” the topology and identity of sub nodes in a daisy-chained network so that changes in the topology may be readily adapted to without substantial interruptions in data transfer in the network.

Abstract: Systems and techniques for line diagnostics. In particular, disclosed herein are systems and techniques for line diagnostics that sense a state of an electrical cable by using multiple, time-spaced stimuli and detecting their signal reflection time at different threshold levels. Information derived from multiple reflections may be used to determine cable characteristics (e.g., “wire short,” “wire open,” “correctly terminated,” etc.). The systems and techniques disclosed herein may advantageously require less complex hardware and implementation algorithms than conventional time domain reflectometry (TDR) approaches, and thus may be implemented in settings in which TDR was previously unsuitable. Further, if a cable issue is detected, the systems and techniques disclosed herein may determine the approximate location of the cable issue along the cable, accelerating correction of the issue.

Abstract: Aspects of the embodiments are directed to auxiliary communication over a pulse density modulated (PDM) interface. Systems utilize a PDM interface between a sigma-delta modulator and a decimation filter to transmit data between devices. In some examples, the PDM interface is used to add non-PDM coded data communication between devices. Devices having a sigma-delta modulator can include microphones and accelerometers. Devices having a decimator can include digital signal processors (DSPs), microcontrollers, and audio codecs. In some examples, non-PDM coded data can be communicated between microphones and a node in a two-wire communication system, between a microphone and a digital signal processor (DSP), or between two microphones.

Abstract: The present disclosure provides a system for data networking. The system includes a plurality of asynchronous data devices including a router device and a set of station devices. The system further includes a main-subordinate communication protocol interface. Each of the plurality of asynchronous data devices is coupled to the main-subordinate communication protocol interface. Data is transmitted over a two-wire bus between the router device and the set of station devices via the main-subordinate communication protocol interface.

Abstract: A log splitter includes a chassis having a support table configured to support a log to be split, a splitter screw having a generally conical shape and mounted to a rotatable screw shaft that is supported by the chassis, and a drive assembly configured to rotate the shaft to impart rotational movement to the splitter screw about a screw axis. The drive assembly includes a motor coupled to the screw shaft via a constant velocity transmission (CVT) (also known as continuously variable transmission). The CVT can provide both high speed and high torque during the splitting process as required to split the log. A fall restriction bar helps restrict a person from accidentally falling onto the splitter screw. An engine-kill bar is pivotally mounted to the chassis. A log-rotation stop mechanism is configured to restrict rotation of a log that gets stuck on the splitter screw.

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

Abstract: Disclosed herein are systems and techniques for audio and lighting control in a bus system. For example, in some embodiments, a bus system may be configured for operation as a light organ and/or to generate sound effects based on accelerometer data.

Abstract: The invention relates to a capacitor (1), particularly an intermediate circuit capacitor for a multiphase system, having a plurality of identical capacitor elements (10), which are connected in parallel and together form the capacitor (1), wherein at least one intermediate space (20) is formed between the capacitor elements (10), at least one intermediate capacitor element (30) is arranged in the intermediate space (20) and is connected in parallel to the capacitor elements (10), and thus together with the capacitor elements (10) forms the capacitor (1).

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.