Abstract: A time to digital converter (TDC) includes a synchronizer configured to receive a stop signal and a master clock signal, wherein the synchronizer is configured to generate a clock stop signal and a counter enable signal. The TDC further includes a coarse counter configured to receive the master clock signal and the counter enable signal, wherein the coarse counter is configured to generate a most significant bits (MSB) signal based on the counter enable signal and the master clock signal. The TDC further includes a delay line counter configured to receive the stop signal and the clock stop signal, wherein the delay line counter is configured to generate a least significant bits (LSB) signal based on the stop signal and the clock stop signal, and the delay line counter is further configured to perform correlated double sampling (CDS).

Abstract: A circuit includes a first digital filter that generates a first output based on a digital input and a first digital output signal. A first digital modulator generates the first digital output signal and a first error output based on the first output and a feedback error output. A second digital modulator generates a second output and a second error output based on the first error output. A second digital filter generates a second digital output signal based on the second output, and a third digital filter generates the feedback error output based on the second error output. The second digital output signal and the second error output are based on the first error output amplified by a predetermined gain.

Abstract: An analog-to-digital converter (ATC) circuit includes a current source; a first amplifier coupled to the current source through a first discharging switch; and a second amplifier coupled to the first amplifier through a second discharging switch; wherein the first amplifier is configured to receive a residue signal of an analog input signal, upon the first discharging switch being turned on, the first amplifier amplifies the residue signal to generate an output signal and simultaneously the current source discharges the residue signal, upon the second discharging switch being turned on, the second amplifier detects when the output signal equals zero so as to determine a discharging time duration of the output signal.

Abstract: A time to digital converter (TDC) includes a synchronizer configured to receive a stop signal and a master clock signal, wherein the synchronizer is configured to generate a clock stop signal and a counter enable signal. The TDC further includes a coarse counter configured to receive the master clock signal and the counter enable signal, wherein the coarse counter is configured to generate a most significant bits (MSB) signal based on the counter enable signal and the master clock signal. The TDC further includes a delay line counter configured to receive the stop signal and the clock stop signal, wherein the delay line counter is configured to generate a least significant bits (LSB) signal based on the stop signal and the clock stop signal, and the delay line counter is further configured to perform correlated double sampling (CDS).

Abstract: An analog-to-digital converter (ADC) that comprises a first ADC stage and a second ADC stage. The first ADC stage comprises a successive approximation register (SAR). The first ADC is configured to convert an analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a digital output signal. The first ADC stage is also configured to generate a residual voltage corresponding to a difference between a voltage value of the analog input signal and the first digital signal. The second ADC stage comprises a plurality of time-to-digital converter (TDC) cells coupled in series. The second ADC is configured to convert the residual voltage into a plurality of second digital signals generated by the TDC cells. The second digital signals correspond to a least-significant-bits (LSB) portion of the digital output signal. The digital output signal is a digital representation of the analog input signal.

Abstract: An analog-to-digital converter (ADC) that comprises a first ADC stage and a second ADC stage. The first ADC stage comprises a successive approximation register (SAR). The first ADC is configured to convert an analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a digital output signal. The first ADC stage is also configured to generate a residual voltage corresponding to a difference between a voltage value of the analog input signal and the first digital signal. The second ADC stage comprises a plurality of time-to-digital converter (TDC) cells coupled in series. The second ADC is configured to convert the residual voltage into a plurality of second digital signals generated by the TDC cells. The second digital signals correspond to a least-significant-bits (LSB) portion of the digital output signal. The digital output signal is a digital representation of the analog input signal.

Abstract: A Class-D amplifier includes an analog-to-digital converter (ADC) having a first input node. The ADC receives a first analog input signal and a first feedback signal at the first input node and generates a first digital signal based on the first analog input signal and the first feedback signal. A digital filter generates a second digital signal based on the first digital signal. An output circuit includes a first output node, the output circuit being configured to generate a first output signal at the first output node based on the second digital signal. A first feedback unit generates the first feedback signal as the first output signal scaled by a gain factor having a constant value in the Z-domain.

Abstract: A Class-D amplifier includes an analog-to-digital converter (ADC), a digital filter, a digital pulse width modulation (PWM) unit, a pre-driver unit, and an output driver. The ADC is configured to receive an input signal and one or more feedback signals, and to generate a first digital signal. The digital filter, the digital PWM unit, and the pre-driver unit are configured to generate control signals based on the first digital signal. The output driver is configured to generate an output signal based on the control signals. A first feedback path is defined as from a first output node of the output driver to a first input node of the ADC; and a second feedback path is defined as from a second output node of the output driver to a second input node of the ADC. The first and second feedback paths are free from a low-pass filtering device.

Abstract: A circuit includes an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a digital filter configured to filter the digital output and a noise shaper. The noise shaper is configured to truncate the filtered digital output and generate a noise shaper output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC) configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.

Abstract: An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a digital-to-analog (D/A) conversion circuit, a comparison circuit and a control circuit. The track-and-hold circuit is configured to output a first signal based on an input signal. The D/A conversion circuit is configured to generate a second signal based on an N-bit logical signal. The comparison circuit is configured to generate a comparison result based on the first signal and the second signal. The control circuit is configured to generate the N-bit logical signal according to N comparison results from the comparison circuit.

Abstract: A circuit includes a first digital filter that generates a first output based on a digital input and a first digital output signal. A first digital modulator generates the first digital output signal and a first error output based on the first output and a feedback error output. A second digital modulator generates a second output and a second error output based on the first error output. A second digital filter generates a second digital output signal based on the second output, and a third digital filter generates the feedback error output based on the second error output. The second digital output signal and the second error output are based on the first error output amplified by a predetermined gain.

Abstract: A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load.

Abstract: An analog-to-digital conversion system includes a track-and-hold unit configured to output an input value; a digital-to-analog (D/A) conversion unit configured to generate a feedback value; a coupling unit configured to generate an error signal value based on the input signal and the feedback value; a loop filter configured to generated a filtered error signal value; a comparison unit configured to generate a comparison result based on the input value minus the summation of the feedback value and the filtered error signal value; and a control unit. The control unit is configured to, during a sampling cycle, set an N-bit logical value accordingly to N comparison results; and to cause the coupling unit to generate the error signal value. N is a positive integer.

Abstract: A Class-D amplifier includes an analog-to-digital converter (ADC), a digital filter, a digital pulse width modulation (PWM) unit, a pre-driver unit, and an output driver. The ADC is configured to receive an input signal and one or more feedback signals, and to generate a first digital signal. The digital filter, the digital PWM unit, and the pre-driver unit are configured to generate control signals based on the first digital signal. The output driver is configured to generate an output signal based on the control signals. A first feedback path is defined as from a first output node of the output driver to a first input node of the ADC; and a second feedback path is defined as from a second output node of the output driver to a second input node of the ADC. The first and second feedback paths are free from a low-pass filtering device.

Abstract: A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a cascaded digital pulse width modulation noise shaper having multiple stages to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal. The cascaded noise shaper stages each operate using the same quantization error signal.

Abstract: A circuit includes a first digital filter H(z), a second digital filler 1 1 + H ? ( z ) , a third digital filter, a first and a second digital modulators, and a gain block. The first digital filter generates a first output based on a digital input and a first digital output signal. The first digital modulator generates the first digital output signal and a first error output based on the first output and a feedback error output. The gain block amplifies the first error output by a predetermined ratio, thereby generating a second error output. The second digital modulator generates a second output and a third error output based on the second error output. The second digital filter generates a second digital output signal based on the second output. The third filter generates the feedback error output based on the third error output.

Abstract: A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load.

Abstract: A circuit includes an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a digital filter configured to filter the digital output and a noise shaper. The noise shaper is configured to truncate the filtered digital output and generate a noise shaper output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC) configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.

Abstract: A circuit includes a first digital filter H(z), a second digital filter 1 1 + H ? ( z ) , a third digital filter, a first and a second digital modulators, and a gain block. The first digital filter generates a first output based on a digital input and a first digital output signal. The first digital modulator generates the first digital output signal and a first error output based on the first output and a feedback error output. The gain block amplifies the first error output by a predetermined ratio, thereby generating a second error output. The second digital modulator generates a second output and a third error output based on the second error output. The second digital filter generates a second digital output signal based on the second output. The third filter generates the feedback error output based on the third error output.

Abstract: An apparatus and method for generating a ramp signal includes applying a constant reference voltage to a reference capacitor and controlling charging or discharging of the reference capacitor with a programmable current generator to provide the ramp signal at a ramp signal node. The method can include, buffering the ramp signal to an output node to drive a load. When generating the ramp signal having a negative slope, the programmable current generator includes a programmable current sink coupled to the ramp signal node. When generating the ramp signal having a positive slope, the programmable current generator includes a programmable current source that is coupled between a positive power supply node and the ramp signal node. When generating the ramp signal having a bidirectional slope, the programmable current generator includes a programmable current source and a programmable current sink.