Abstract: A circuit portion comprises a signal generator, clocked by a clock signal, for generating an alternating logic signal comprising a repeated sequence of alternating logic transitions. A circuit sub-portion introduces a delay to the alternating logic signal. An edge-travel detector samples the delayed alternating logic signal and outputs an edge-travel signal representative of a timing of a logic transition in the alternating logic signal with respect to the clock signal. A mask block compares the edge-travel signal with a mask signal to determine whether the timing of the logic transition matches one or more candidate timings, and outputs a comparison signal in dependence on this determination.