Abstract: The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword.

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first memory block and writing a second portion of the codeword in a second memory block. The first memory block and the second memory block can be different memory blocks. The first portion of the codeword can be written in a different location in the first memory block than the second portion of the codeword is written in the second memory block.

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract: Error correction in a disk drive is performed by error correction circuitry which accepts data read from a data storage medium. The error correction circuitry performs both block error correction in a first data domain and sector error correction in a second data domain. A sector FIFO buffer is used to facilitate the error correction in real time, or “on-the-fly.” The sector FIFO buffer also enables conversion of the corrected data to the first data domain. The error correction circuitry also generates an ECC block comprising a plurality of sectors and writes the ECC block. The circuitry generates a tag prior to writing the ECC block and adds the tag to each of a plurality of sectors. During a read operation, the circuitry detects a write disruption when the tags for all of the plurality of sectors in the ECC block are not identical.

Abstract: A device can receive information to be stored in a first part of a first portion of a block, read previously-stored information from a second part, and store the specified information in the first part and simulate storage of the previously-stored information in the second part while generating error detection information which is then stored in a second portion of the block. The device can read a specified subset of sections in a block, use part of each section to detect and/or correct an error in another part thereof, while avoiding reading the error detection information unless a section in the subset has an uncorrected error. Detected errors are corrected with successive correction stages, while maintaining for each section being processed in the stages a count of the number of other sections which are thereafter read in succession without error.

Abstract: A device can receive information to be stored in a first part of a first portion of a block, read previously-stored information from a second part, and store the specified information in the first part and simulate storage of the previously-stored information in the second part while generating error detection information which is then stored in a second portion of the block. The device can read a specified subset of sections in a block, use part of each section to detect and/or correct an error in another part thereof, while avoiding reading the error detection information unless a section in the subset has an uncorrected error. Detected errors are corrected with successive correction stages, while maintaining for each section being processed in the stages a count of the number of other sections which are thereafter read in succession without error.

Abstract: Description tables can be linked to a kernel to form a device driver. The description tables can be device description tables and adapter description tables. The kernel is operating system dependent. The description tables are operating system independent and can be linked to other kernels for other operating systems. A library of kernels for different operating systems can share a common set of kernel requests.

Abstract: Description tables can be linked to a kernel to form a device driver. The description tables can be device description tables and adapter description tables. The kernel is operating system dependent. The description tables are operating system independent and can be linked to other kernels for other operating systems. A library of kernels for different operating systems can share a common set of kernel requests.

Abstract: The present invention includes a method, apparatus and disk format for implementation of the same to provide fault tolerant detection of ID fields for data sectors in order to eliminate errors caused by mis-alignment and mis-detection of hard sector marks. Logic is provided to initiate a time-out count at the completion of a hard sector count. The time-out count is specified to be a period of time within which a hard sector mark should be detected. If the time out count counts down and a hard sector mark is not detected, then a possible error situation arises and the fault tolerant process is initiated to compensate for the lack of detection of a hard sector mark. Thus, at the end of the time-out count, a small burst count is started.