Abstract: An asynchronous time division communication system having at least one station including a buffer and an associated processor for writing data packets into said buffer at a sending clock frequency, and for reading data packets from said buffer at a receiving clock frequency. The processor is further capable of assessing the real packet filling level of the buffer and adjusting the receiving clock frequency in corresponding relationship to the assessed real packet filling level. The processor calculates a mean packet filling level after a measured time has elapsed by using the mean of m successively assessed real packet filling levels of said buffer and using the calculated mean packet filling level for adjusting the receiving clock frequency.

Abstract: The data communication system includes a packet switching network (PSN), a plurality of user circuits (UC), and a plurality of sender/receiver circuits (SEND/REC). Each sender/receiver circuit is coupled between the network (PSN) and at least one of the user circuits (UC). Each sender circuit (SEND) of an originating sender/receiver circuit being able to transmit packets received from an originating user circuit on the network and each receiver circuit (REC) of a destination sender/receiver circuit coupled to a destination user circuit including a timing circuit (TC) to subject received packets to a delay (T). This delay (T) is so chosen (Tm) that with a predetermined probability the error in a delayed packet is always less than a predetermined value (A).