Abstract: One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

Abstract: One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

Abstract: Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.

Abstract: Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.

Abstract: Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.

Abstract: A programmable logic device with fabric regularity is disclosed. For example, the programmable logic device may include a plurality of similar heterogeneous logic blocks. A user's design may be implemented within a first group of heterogeneous logic blocks. The user's design may be moved or copied to a second group of heterogeneous logic blocks. More specifically, routing, timing, and/or placement information associated with the implementation of the users design in the first group of heterogeneous logic blocks may be used to implement the user's design in the second group of heterogeneous logic blocks.

Abstract: An integrated circuit (IC) die and integrated circuit (IC) chip packages having such dies are described that leverage the symmetry of the arrangement of micro-bumps to advantageously reduce interposer cost and size requirements. In one example, an integrated circuit (IC) die is provided. The IC die includes a die body, a plurality of programmable tiles disposed in the die body, and a plurality of micro-bumps disposed in the die body. The die body includes a front face connecting a bottom exterior surface and a top exterior surface. A centerline of the die body is perpendicular to the front face and bifurcates the top exterior surface. At least two of the programmable tiles are of a common type. The micro-bumps adjacent the front face and coupled to the common type of programmable tiles have a substantially symmetrical orientation relative to a symmetry axis. The symmetry axis being one of (a) collinear with the centerline of the die body, or (b) parallel to the centerline of the die body.

Abstract: A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data storage node of a plurality of data storage nodes by latching data at the first node using the reference input signal; and maintaining a state of a second data storage node of the plurality of data storage nodes by latching data at the second data storage node using the delayed input signal. A circuit for preventing an unintentional state change in a data storage node of a latch is also disclosed.

Abstract: A method and apparatus is provided for the implementation of a measurement and adjustment mechanism within a semiconductor die that facilitates adjustment of the magnitude of voltage generated by one or more voltage reference generation circuits on the die. In a first embodiment, the output voltage magnitude of a bandgap reference circuit may be measured and adjusted. In a second embodiment, the output voltage magnitude of a voltage regulator circuit may be measured and adjusted. Programmable circuit elements, such as programmable resistors, may first be programmed during a configuration event of the die to determine the optimal configuration settings of the one or more voltage reference generation circuits. The optimal configuration settings are then used to program the state of one or more eFuses to maintain the optimal configuration settings for the duration of the semiconductor die's lifetime.

Abstract: An integrated circuit including a voltage generator for generating a body bias voltage is described. The voltage generator includes a charge source and a voltage regulator coupled to the charge source. Transistors are coupled to the charge source to receive the body bias voltage from the voltage generator.

Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

Abstract: A voltage supply circuit having variable drive strength can optionally be used to provide improved phase margin in an integrated circuit. A bandgap circuit drives an operational amplifier, with the second input of the operational amplifier being a regulated voltage node. The operational amplifier drives multiple pull-ups in a pull-up network coupled to the regulated voltage node, of which the different pull-ups can be separately enabled to control the effective channel width of the pull-up network. In some embodiments, a control circuit (e.g., one or two additional operational amplifiers driving a counter) accepts the output of the operational amplifier as an input signal and provides multiple enable signals to the pull-up network.

Abstract: Circuits and methods of implementing flip-flops in dual-output lookup tables (LUTs). A flip-flop is implemented by programming a dual-output LUT to include a first function implementing a master latch and a second function implementing a slave latch. An output of the master latch is provided at a first output terminal of the LUT, and an output of the slave latch is provided at a second output terminal of the LUT. The output of the master latch (the first output of the LUT) is coupled to a first input terminal of the LUT, where it drives both the first and second functions. The output of the slave latch (the second output of the LUT) is coupled to a second input terminal of the LUT, where it drives the second function. A clock signal is provided to both first and second functions via a third input terminal of the LUT.

Abstract: A lookup table (LUT) is programmable to function as a flip-flop. The LUT includes a plurality of memory cells, a plurality of transmission gates, and first and second logic gates. The transmission gates are coupled between the memory cells and an output terminal of the LUT to form a multiplexer circuit selecting one of a plurality of values stored in the memory cells and providing the selected value to the output terminal. First and second logic gates are included in two of the paths through the multiplexer, also providing first and second feedback paths within the LUT. These feedback paths enable the programmable implementation of first and second latches that form the flip-flop. Another subset of the memory cells can be optionally used to implement a function that drives the data input of the flip-flop.

Abstract: Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

Abstract: Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required to implement an effective metal-to-metal capacitor, compared (for example) to the size of the static memory cell itself. The configuration memory cells of PLDs are typically placed next to other logic (e.g., the configurable elements controlled by the configuration memory cells) that can be overlain by the metal-to-metal capacitors. Therefore, metal-to-metal capacitors can be used in PLD configuration memory cells where they might be impractical in simple memory arrays. However, metal-to-metal capacitors can also be applied to integrated circuits other than PLDs.

Abstract: Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

Abstract: A memory element structure in a programmable logic device (PLD) reduces power consumption by placing the memory element in a power save mode when the memory element is unused in a user design implemented in the PLD. An exemplary structure includes a multiplexer driving a memory element. A multiplexer control circuit controls the multiplexer, and also drives a clock control circuit for the memory element. When the memory element is used by a user design implemented in the PLD, one of the data inputs is selected to drive the memory element. The controlled functions occur normally in the memory element. When the memory element is not used by the user design, none of the data inputs is selected, an input control signal is intercepted by the clock control circuit, and the controlled functions do not occur in the memory element, reducing the power consumption of the unused memory element.