Patents by Inventor Martin Langhammer

Martin Langhammer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9684488
    Abstract: Circuitry accepting a first input value and a second input value, and outputting (a) a first sum involving the first input value and the second input value, and (b) a second sum involving the first input value and the second input value, includes a first adder circuit, a second adder circuit, a compressor circuit and a preprocessing stage. The first input value and the second input value are input to the first adder circuit to provide the first sum. The first input value and the second input value are input to the preprocessing stage to provide inputs to the compressor circuit, which provides first and second compressed output signals which in turn are input to the second adder circuit to provide the second sum. The preprocessing stage may include circuitry to programmably zero the first input value, so that the first sum is programmably settable to the second input value.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: June 20, 2017
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Publication number: 20170115958
    Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.
    Type: Application
    Filed: October 21, 2015
    Publication date: April 27, 2017
    Inventor: Martin Langhammer
  • Patent number: 9619207
    Abstract: Galois-field reduction circuitry for reducing a Galois-field expansion value using an irreducible polynomial includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective expansion bit position. Gates select ones of said the plurality of memories corresponding to ones of the respective expansion bit positions that contain ‘1’, and an exclusive-OR gate combines outputs of the gates that select. A specialized processing block includes a multiplier stage, and an input stage upstream of the multiplier stage, with such Galois-field reduction circuitry in the input stage with its output selectably connectable to the multiplier stage and selectably connectable to an output of the specialized processing block. A programmable integrated circuit device includes a plurality of such specialized processing blocks, and additional multiplier and additional exclusive OR gates for concatenating a plurality of specialized processing blocks.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: April 11, 2017
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 9613232
    Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of vector (dot product) operations, FIR filters, or sum-of-product operations.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: April 4, 2017
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 9606608
    Abstract: Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a first multiplier that generates a first partial product associated with a first set of bit locations and a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations. The device further includes a switching circuitry to deactivate the first multiplier to reduce an amount of power consumed by the programmable integrated circuit device.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 28, 2017
    Assignee: ALTERA CORPORATION
    Inventor: Martin Langhammer
  • Patent number: 9600278
    Abstract: A specialized processing block on a programmable integrated circuit device includes a first floating-point arithmetic operator stage, and a floating-point adder stage having at least one floating-point binary adder. Configurable interconnect within the specialized processing block routes signals into and out of each of the first floating-point arithmetic operator stage and the floating-point adder stage. The block has a plurality of block inputs, at least one block output, a direct-connect input for connection to a first other instance of the specialized processing block, and a direct-connect output for connection to a second other instance of the specialized processing block. A plurality of instances of the specialized processing block are together configurable as a binary or ternary recursive adder tree.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 21, 2017
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 9594928
    Abstract: Encryption/authentication circuitry includes an encryption portion having a first number of encryption lanes, each encryption lane including a plurality of encryption stages, and keyspace circuitry including a plurality of key lanes corresponding to a predetermined maximum number of channels. Each key lane has key storage stages corresponding to the encryption stages, and includes key memories for the predetermined maximum number of channels. Key channel selection circuitry for each stage selects a key from among the key memories at that stage. An authentication portion includes a second number of authentication lanes, hash key storage for the predetermined maximum number of channels, partial hash state storage for the predetermined number of channels, and hash channel selection circuitry.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: March 14, 2017
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 9582686
    Abstract: Methods, circuits, and apparatus are provided an FPGA user, ASIC designer, or the like the ability to program a unique ID per each circuit into a memory, such as a non-volatile one-time programmable memory bank on an FPGA. This unique ID is secure such that no one else can replicate it on another part, thus keeping it unique to the user for which it was intended. An encryption engine receives plaintext and produces the unique ID that is stored in memory that is designed to only be writeable through the encryption engine. Thus, the FPGA/ASIC designer can track who is the customer they sold this part to or who the last authorized user is.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: February 28, 2017
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Juju Joyce
  • Patent number: 9583218
    Abstract: Integrated circuits such as application specific integrated circuits or programmable logic devices may include sequential elements such as configurable register circuitry. Such configurable register circuitry may operate as independent registers controlled by selectable clock signals or as a single register with error detection and error correction capabilities. For example, the configurable register circuitry when operated as single register with error detection and error correction circuitry may detect and correct runtime errors caused by manufacturing and environmental variations, thereby allowing an increase in the clock rate that controls the register. If desired, the configurable register circuitry may be configured to detect single event upsets, which may enable the implementation of safe finite state machines.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: February 28, 2017
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Martin Langhammer
  • Patent number: 9575725
    Abstract: A specialized processing block on an integrated circuit is provided that performs pipelined floating-point accumulation operations. The specialized processing block may be configured to perform one accumulation operation and produce the result of the accumulation at every other clock cycle. Alternatively, the specialized processing block may be configured to perform two independent accumulation operations and produce the result of each of the accumulation operations alternating at consecutive clock cycles. The specialized processing block may include a dedicated three-input floating-point adder circuit. The specialized processing block may also fuse two independent two-input floating-point adder circuits to be configurable as two independent two-input floating-point adders or one three-input floating-point adder.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: February 21, 2017
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 9552190
    Abstract: In accordance with some embodiments, a floating point number datapath circuitry, e.g., within an integrated circuit programmable logic device is provided. The datapath circuitry may be used for computing a rounded absolute value of a mantissa of a floating point number. The floating point datapath circuitry may have only a single adder stage for computing a rounded absolute value of a mantissa of the floating point number based on one or more bits of an unrounded mantissa of the floating point number. The unrounded and rounded mantissas may include a sign bit, a sticky bit, a round bit, and/or a least significant bit, and/or other bits. The unrounded mantissa may be in a format that includes negative numbers (e.g., 2's complement) and the rounded mantissa may be in a format that may include a portion of the floating point number represented as a positive number, (e.g., signed magnitude).
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 24, 2017
    Assignee: ALTERA CORPORATION
    Inventors: Martin Langhammer, Bogdan Pasca
  • Patent number: 9553591
    Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: January 24, 2017
    Assignee: ALTERA CORPORATION
    Inventors: Steven Perry, Martin Langhammer, Richard Maiden
  • Patent number: 9552189
    Abstract: Circuitry that performs floating-point operations on an integrated circuit is provided. The circuitry may execute a floating-point operation by decomposing the floating-point operation into multiple steps and decomposing the floating-point number on which to perform the floating-point operation into multiple portions. The circuitry may include storage circuits that store at least some results of the multiple steps, and memory access operations may be performed using some portions of the floating-point number. The circuitry may use arithmetic floating-point and arithmetic fixed-point circuits to implement Taylor series expansion circuits that may perform a subset of the multiple steps, thereby reducing the complexity of the subset of these steps.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: January 24, 2017
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Bogdan Pasca
  • Publication number: 20160373138
    Abstract: A system includes an encoding circuit, a line quality monitor circuit, and a controller circuit. The encoding circuit generates a first data signal indicating encoded data using a first forward error correction code. The line quality monitor circuit generates an indication of a line quality of a second data signal using an eye monitor circuit that monitors the second data signal. The controller circuit causes the encoding circuit to generate encoded data in the first data signal using a second forward error correction code in response to a change in the indication of the line quality of the second data signal.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Applicant: ALTERA CORPORATION
    Inventors: Peng Li, Martin Langhammer, Jon Long
  • Publication number: 20160373134
    Abstract: Decoder circuitry for an input channel having a data rate, where a codeword on the input channel includes a plurality of symbols, includes options to provide a first output channel having that data rate, and a plurality of second output channels having slower data rates. The decoder circuitry includes syndrome calculation circuitry, polynomial calculation circuitry, and search-and-correct circuitry. The syndrome calculation circuitry includes finite-field multipliers for multiplying each symbol by a power of a root of the field. Each multiplier other than a first multiplier multiplies a symbol by a higher power of the root than an adjacent multiplier. First-level adders add outputs of a number of groups of multipliers. A second-level adder adds outputs of the first-level adders to be accumulated as syndromes of the first output channel. Another plurality of accumulators accumulates outputs of the first-level adders, which after scaling, are syndromes of the second output channels.
    Type: Application
    Filed: January 4, 2016
    Publication date: December 22, 2016
    Inventor: Martin Langhammer
  • Patent number: 9519807
    Abstract: Encryption/authentication circuitry includes an authentication portion operating on a plurality of lanes of encrypted data spanning a number of channels, and including hash constant storage for a predetermined maximum number of channels, and partial hash selection circuitry for determining, for each respective lane, a respective hash index into the hash constant storage. Wind-down mode detection circuitry also is described, as well as a method of operating such circuitry also is provided.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 13, 2016
    Assignee: ALTERA CORPORATION
    Inventor: Martin Langhammer
  • Publication number: 20160358638
    Abstract: An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion of the functional blocks on the integrated circuit may operate at a 2× data rate that is double the normal data rate. To support this type of architecture, the integrated circuit may include clock generation circuitry that is capable of providing double pumped clock signals having clock pulses at rising and falling edges of the core clock signal, data concentration circuitry at the input of the 2× functional blocks, and data spreading circuitry at the output of the 2× functional blocks.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 8, 2016
    Inventors: Martin Langhammer, Dana How
  • Patent number: 9507565
    Abstract: Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: November 29, 2016
    Assignee: ALTERA CORPORATION
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Hyun Yi
  • Publication number: 20160342422
    Abstract: Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Inventor: Martin Langhammer
  • Publication number: 20160344373
    Abstract: Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder that calculates the output sum based least in part on the product value.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Inventors: Martin Langhammer, Simon Peter Finn