Abstract: A multi-domain, distributed arbitration system, and a method performed by a plurality of arbiters to control arbitration of requests for a multiprocessor system bus. The requests are generated by a plurality of nodes coupled to the multiprocessor system bus. The requests are presented on a plurality of arbitration request lines. Each node comprises one of the arbiters such that each arbiter is associated with a corresponding node. A plurality of domains are created by the arbiters based on a bit-wise combination of the requests on the arbitration lines. A priority is assigned to each domain relative to the other domains. Each arbiter monitors the requests on the arbitration request lines and generates an i.sub.-- win result that indicates whether or not the associated node is an overall arbitration winner if a request from that node is pending. In addition, the arbiters generate a who.sub.-- won result that indicates which node was the overall arbitration winner according to the assigned priorities.

Abstract: A multiprocessing system that uses read resources to track cache coherent split transactions on its main system bus. Pending reads are tracked by being associated with read resources. When a read request is issued, it occupies the first available read resource. A pending read request will occupy a read resource until a corresponding read response appears on the bus. If all read resources are filled, future read requestors must wail until a read resource becomes available.

Abstract: A dynamic random access memory (DRAM) single in-line memory module (SIMM) having optimized physical dimensions achieves high speed and high storage capacity. The DRAM SIMM has a printed circuit board with a multi-contact connector, a plurality of DRAM sets, each set having a plurality of DRAM chips mounted on the printed circuit board, and a plurality of buffers which are also mounted on the printed circuit board. The number of buffers is equal to the number of DRAM sets. Various standard DRAM chips can be used on the SIMM to achieve different performance and storage capacity, while maintaining plug compatibility of the multi-contact connector with a memory board. The buffers buffer the control and address signals for the DRAM chips, which is necessary to keep control and address signal integrity due to the number of DRAMS. The buffers permit each DRAM to receive the necessary control and address signals in a more synchronized fashion, so that relative delays are well controlled.