Patents by Inventor Martin Mischitz

Martin Mischitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11488921
    Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: November 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Ali Roshanghias, Alfred Binder, Barbara Eichinger, Stefan Karner, Martin Mischitz, Rainer Pelzer
  • Patent number: 11329021
    Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Fabian Craes, Barbara Eichinger, Martin Mischitz, Frederik Otto, Fabien Thion
  • Publication number: 20210098410
    Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 1, 2021
    Inventors: Ali Roshanghias, Alfred Binder, Barbara Eichinger, Stefan Karner, Martin Mischitz, Rainer Pelzer
  • Publication number: 20200161269
    Abstract: A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 21, 2020
    Applicant: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Fabian Craes, Barbara Eichinger, Martin Mischitz, Frederik Otto, Fabien Thion
  • Patent number: 10580753
    Abstract: According to an embodiment of a method of manufacturing a plurality of semiconductor devices on a wafer, the method includes forming a structure layer comprising a plurality of same semiconductor device structures and providing a protective layer on the structure layer. The protective layer on a first one of the plurality of semiconductor device structures differs from the protective layer on a second one of the plurality of semiconductor device structures.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Martin Mischitz, Harald Huber, Michael Knabl, Claudia Sgiarovello, Caterina Travan, Andrew Wood
  • Patent number: 10515910
    Abstract: According to various embodiments, a semiconductor device may include: a contact pad; a metal clip disposed over the contact pad; and a porous metal layer disposed between the metal clip and the contact pad, the porous metal layer connecting the metal clip and the contact pad with each other.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 24, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mischitz, Kurt Matoy
  • Patent number: 10373868
    Abstract: According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: August 6, 2019
    Assignees: INFINEON TECHNOLOGIES AUSTRIA AG, TECHNISCHE UNIVERSITAET GRAZ
    Inventors: Martin Mischitz, Markus Heinrici, Michael Roesner, Oliver Hellmund, Caterina Travan, Manfred Schneegans, Peter Irsigler, Friedrich Kroener
  • Patent number: 10340197
    Abstract: A die includes a plurality of dielectric landings and a conductive material distributed across one or more of the plurality of dielectric landings. Each one of the plurality of dielectric landings electrically separates two conductive landings associated with the one of the plurality of dielectric landings. The conductive material establishes an electrical connection between the two conductive landings associated with the one or more of the plurality of dielectric landings.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
  • Patent number: 10269635
    Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a liquid is provided on a selected portion of the wafer to selectively alter at least one circuit element within the at least one of the plurality of semiconductor device structures.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: April 23, 2019
    Assignee: Infineon Technologies AG
    Inventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
  • Publication number: 20190027464
    Abstract: According to an embodiment of a method of manufacturing a plurality of semiconductor devices on a wafer, the method includes forming a structure layer comprising a plurality of same semiconductor device structures and providing a protective layer on the structure layer. The protective layer on a first one of the plurality of semiconductor device structures differs from the protective layer on a second one of the plurality of semiconductor device structures.
    Type: Application
    Filed: July 21, 2017
    Publication date: January 24, 2019
    Applicant: Infineon Technologies AG
    Inventors: Martin Mischitz, Harald Huber, Michael Knabl, Claudia Sgiarovello, Caterina Travan, Andrew Wood
  • Patent number: 9929111
    Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: March 27, 2018
    Assignee: Infineon Technologies AG
    Inventors: Martin Mischitz, Markus Heinrici, Barbara Eichinger, Manfred Schneegans, Stefan Krivec
  • Patent number: 9911686
    Abstract: A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: March 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Andreas Meiser, Martin Mischitz, Michael Roesner, Michael Pinczolits
  • Patent number: 9899277
    Abstract: A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: February 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
  • Patent number: 9844134
    Abstract: A device comprises a base element and a metallization layer over the base element. The metallization layer comprises pores and has a varying degree of porosity, the degree of porosity being higher in a portion adjacent to the base element than in a portion remote from the base element.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: December 12, 2017
    Assignee: Infineon Technologies AG
    Inventors: Martin Mischitz, Markus Heinrici, Stefan Schwab
  • Patent number: 9818602
    Abstract: A method a described which includes depositing a first component of a multicomponent system by means of an inkjet process, and depositing a second component of the multicomponent system by means of an inkjet process.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 14, 2017
    Assignees: Infineon Technologies AG, Technische Universit├Ąt Graz
    Inventors: Stefan Schwab, Markus Heinrici, Rafael Janski, Susanne Kraeuter, Martin Mischitz
  • Patent number: 9793119
    Abstract: According to various embodiments, a method of processing a substrate may include: disposing a viscous material over a substrate including at least one topography feature extending into the substrate to form a protection layer over the substrate; adjusting a viscosity of the viscous material during a contacting period of the viscous material and the substrate to stabilize a spatial distribution of the viscous material as disposed; processing the substrate using the protection layer as mask; and removing the protection layer after processing the substrate.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: October 17, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mischitz, Markus Heinrici, Florian Bernsteiner
  • Patent number: 9786568
    Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
  • Publication number: 20170271216
    Abstract: A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Applicant: Infineon Technologies AG
    Inventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood
  • Patent number: 9768023
    Abstract: According to various embodiments, a method of processing a substrate may include: disposing a viscous material over a substrate including at least one topography feature extending into the substrate to form a protection layer over the substrate; adjusting a viscosity of the viscous material during a contacting period of the viscous material and the substrate to stabilize a spatial distribution of the viscous material as disposed; processing the substrate using the protection layer as mask; and removing the protection layer after processing the substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 19, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mischitz, Markus Heinrici, Florian Bernsteiner
  • Publication number: 20170243795
    Abstract: A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Applicant: Infineon Technologies AG
    Inventors: Claudia Sgiarovello, Martin Mischitz, Andrew Wood