Abstract: Embodiments disclosed herein include semiconductor die with overlay marks, electronic devices that include semiconductor dies with overlay marks, and methods of measuring overlay. In one embodiment, a semiconductor die includes multiple overlay marks, including a first overlay mark and a second overlay mark. The first overlay mark is at a first position on the semiconductor die and includes a first set of patterns with a first orientation. The second overlay mark is at a second position on the semiconductor die and includes a second set of patterns with a second orientation. The first position of the first mark and the second position of the second mark are non-overlapping. In addition, the first orientation of the patterns in the first mark is substantially orthogonal to the second orientation of the patterns in the second mark.

Abstract: Techniques for forming overlay metrology marks are disclosed. In the illustrative embodiment, a first overlay metrology mark is on a first layer of a semiconductor wafer, and a second metrology mark is formed on a second layer above the first layer. The overlay metrology marks are embodied as a series of grating lines. Looking downward at the overlay metrology marks, the two metrology marks form a moire pattern, with the light and dark regions of the moire pattern moving as the relative positions of the overlay metrology marks move. In the illustrative embodiment, at least one of the overlay metrology marks has non-uniform grating line spacing. As a result, the moire pattern is not identical if the overlay metrology mark is shifted by one grating line, allowing for a wider range of overlay errors to be detected.

Abstract: Pattern recognition targets including regions of one or more layers of gratings are used for semiconductor fabrication wafer alignment. Grates of the gratings are below the resolution limit of the alignment microscopes, and have dimensions compatible with design rules applied to actual device circuitry. Targets may be located by the contrast of light reflected and diffracted back from the regions and through a numerical aperture of the microscope. Target contrast may be achieved by controlling the diffractive properties of the regions. A grating with a pitch that causes a significant amount light to diffract out of the numerical aperture will appear darker, while a grating with a pitch that produces minimal diffraction with appear much brighter. Moreover, for a darker causing pitch, a region of layers gratings having grates stacked on each other can appear even darker, while a region having layers of grates interleaved can appear even brighter.

Abstract: Pattern recognition targets including regions of one or more layers of gratings are used for semiconductor fabrication wafer alignment. Grates of the gratings are below the resolution limit of the alignment microscopes, and have dimensions compatible with design rules applied to actual device circuitry. Targets may be located by the contrast of light 0racted back from the regions and through a numerical aperture of the microscope. Target contrast may be achieved by controlling the diffractive properties of the regions. A grating with a pitch that causes a significant amount light to diffract out of the numerical aperture will appear darker, while a grating with a pitch that produces minimal diffraction with appear much brighter. Moreover, for a darker causing pitch, a region of layers gratings having grates stacked on each other can appear even darker, while a region having layers of grates interleaved can appear even brighter.

Abstract: Some embodiments of the present invention include implanting and annealing polysilicon lines to form a silicide blocking layer that may inhibit silicide formation. The silicide blocking layer may facilitate fabrication of polysilicon resistors.