Patents by Inventor Martin Ohmacht

Martin Ohmacht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transactional lock elision with delayed lock checking
    Patent number: 11625286
    Abstract: A computer-implemented method includes the following operations. A transactional lock elision transaction including a critical section is executed. The critical section is processed. After the processing of the critical section and prior to a commit point in the transactional lock elision transaction, a status of a lock is checked. Responsive to a determination that a status of the lock is free, a result of the transactional lock elision transaction is committed.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 11, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maged M. Michael, Marcel Mitran, Martin Ohmacht, Kai-Ting Amy Wang
  • Global virtual address space consistency model
    Patent number: 11288194
    Abstract: An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 29, 2022
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Johns, James A. Kahle, Martin Ohmacht, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Alessandro Morari, James C. Sexton, Patrick D. Siegl
  • INTEGRATED CIRCUITS WITH PROGRAMMABLE GATE TIMING SIGNAL GENERATION FOR POWER CONVERTERS AND APPARATUS COMPRISING THE SAME
    Publication number: 20200244166
    Abstract: An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Inventors: Xin Zhang, Todd Edward Takken, Chung-shiang Wu, Robert Matthew Senger, Rudolf Adriaan Haring, Martin Ohmacht
  • Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same
    Patent number: 10707755
    Abstract: An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Zhang, Todd Edward Takken, Chung-shiang Wu, Robert Matthew Senger, Rudolf Adriaan Haring, Martin Ohmacht
  • GLOBAL VIRTUAL ADDRESS SPACE CONSISTENCY MODEL
    Publication number: 20200192799
    Abstract: An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Charles R. Johns, James A. Kahle, Martin Ohmacht, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Alessandro Morari, James C. Sexton, Patrick D. Siegl
  • TRANSACTIONAL LOCK ELISION WITH DELAYED LOCK CHECKING
    Publication number: 20190188054
    Abstract: A computer-implemented method includes the following operations. A transactional lock elision transaction including a critical section is executed. The critical section is processed. After the processing of the critical section and prior to a commit point in the transactional lock elision transaction, a status of a lock is checked. Responsive to a determination that a status of the lock is free, a result of the transactional lock elision transaction is committed.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Inventors: Maged M. Michael, Marcel Mitran, Martin Ohmacht, Kai-Ting Amy Wang
  • Transactional lock elision with delayed lock checking
    Patent number: 10275290
    Abstract: A computer-implemented method includes the following operations. A transactional lock elision transaction including a critical section is executed. The critical section is processed. After the processing of the critical section and prior to a commit point in the transactional lock elision transaction, a status of a lock is checked. Responsive to a determination that a status of the lock is free, a result of the transactional lock elision transaction is committed.
    Type: Grant
    Filed: August 14, 2016
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maged M. Michael, Marcel Mitran, Martin Ohmacht, Kai-Ting Amy Wang
  • Combined group ECC protection and subgroup parity protection
    Patent number: 10140179
    Abstract: A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alan Gara, Dong Chen, Philip Heidelberger, Martin Ohmacht
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Store operations to maintain cache coherence
    Patent number: 9760487
    Abstract: In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Constantinos Evangelinos, Ravi Nair, Martin Ohmacht
  • Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses
    Patent number: 9733831
    Abstract: In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: August 15, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Martin Ohmacht
  • Store operations to maintain cache coherence
    Patent number: 9720832
    Abstract: In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: August 1, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Constantinos Evangelinos, Ravi Nair, Martin Ohmacht
  • Transactional lock elision with delayed lock checking
    Patent number: 9529838
    Abstract: Avoiding data conflicts includes initiating a transactional lock elision transaction containing a critical section, executing the transactional lock elision transaction including the critical section, and checking a status of a lock prior to a commit point in the transactional lock elision transaction executing, wherein the checking the status occurs after processing the critical section. A determination of whether the status of the lock checked is free is made and responsive to a determination the lock checked is free, a result of the transactional lock elision transaction is committed.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Maged M. Michael, Marcel Mitran, Martin Ohmacht, Kai-Ting Amy Wang
  • TRANSACTIONAL LOCK ELISION WITH DELAYED LOCK CHECKING
    Publication number: 20160371128
    Abstract: A computer-implemented method includes the following operations. A transactional lock elision transaction including a critical section is executed. The critical section is processed. After the processing of the critical section and prior to a commit point in the transactional lock elision transaction, a status of a lock is checked. Responsive to a determination that a status of the lock is free, a result of the transactional lock elision transaction is committed.
    Type: Application
    Filed: August 14, 2016
    Publication date: December 22, 2016
    Inventors: Maged M. Michael, Marcel Mitran, Martin Ohmacht, Kai-Ting Amy Wang
  • Cache as point of coherence in multiprocessor system
    Patent number: 9507647
    Abstract: In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Matthias A. Blumrich, Luis H. Ceze, Dong Chen, Alan Gara, Phlip Heidelberger, Martin Ohmacht, Burkhard Steinmacher-Burow, Xiaotong Zhuang
  • Multiprocessor system with multiple concurrent modes of execution
    Patent number: 9501333
    Abstract: A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Daniel Ahn, Luis H. Ceze, Dong Chen Chen, Alan Gara, Philip Heidelberger, Martin Ohmacht
  • Transactional lock elision with delayed lock checking
    Patent number: 9460145
    Abstract: Avoiding data conflicts includes initiating a transactional lock elision transaction containing a critical section, executing the transactional lock elision transaction including the critical section, and checking a status of a lock prior to a commit point in the transactional lock elision transaction executing, wherein the checking the status occurs after processing the critical section. A determination of whether the status of the lock checked is free is made and, responsive to a determination the lock checked is free, a result of the transactional lock elision transaction is committed.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: October 4, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maged M. Michael, Marcel Mitran, Martin Ohmacht, Kai-Ting Amy Wang
  • STORE OPERATIONS TO MAINTAIN CACHE COHERENCE
    Publication number: 20160283378
    Abstract: In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
    Type: Application
    Filed: June 19, 2015
    Publication date: September 29, 2016
    Inventors: Constantinos Evangelinos, Ravi Nair, Martin Ohmacht
  • STORE OPERATIONS TO MAINTAIN CACHE COHERENCE
    Publication number: 20160283377
    Abstract: In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Constantinos Evangelinos, Ravi Nair, Martin Ohmacht
  • Code versioning for enabling transactional memory promotion
    Patent number: 9405596
    Abstract: Code versioning for enabling transactional memory region promotion may include receiving a portion of candidate source code; outlining the portion of candidate source code received for parallel execution; wrapping a critical region with entry and exit routines to enter into a speculation sub-process, wherein the entry and exit routines also gather conflict statistics at run time; and generating an outlined code portion comprising multiple loop versions using a processor.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: August 2, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Hans Boettiger, Yaoqing Gao, Martin Ohmacht, Kai-Ting Amy Wang