Abstract: Transient signals resulting from format changes in a signal processing circuit that cause audible popping and clicking noises are simply and efficiently eliminated by disabling handling of data samples during changes between data formats. The transient signals are eliminated in a signal processor circuit that includes a buffer for storing digital data samples and a circuit for eliminating format-dependent transients in a signal processor connected to the buffer. The digital data samples are selectively formatted in a plurality of data formats. The circuit for eliminating format-dependent transients includes a sample formatter connected to the buffer that receives digital data samples from the buffer and selectively modifies the digital data samples from a first data format to a second data format of the plurality of data formats.

Abstract: A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Abstract: This invention is for a single monolithic audio processing integrated circuit which includes a synthesizer module, a CODEC module and an external serial data port in the CODEC module for bi-directional serial data communication between the CODEC module and an external serial data device, such as a digital signal processor. A serial data path between the synthesizer module and the CODEC module is also included.

Abstract: A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data.

Abstract: A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.

Abstract: A stereo audio CODEC, including means for performing D/A and A/D conversions, means for reducing digitally induced noise during attenuation/gain changes, data format conversion means, analog and digital filtering means, analog mixing means, on-chip 16-sample, 32-bit wide record and playback FIFOs, serial interface with external serial DSP, large local memory for supplementing on-chip record and playback FIFOs, control registers, register data bus and synthesizer DAC.