Abstract: A method for testing a memory area. The method includes jumping from a destination address to a source address, reading a data word at the source address after jumping to the source address, and examining the data word. The source address was determined based on a static test.

Abstract: A method for testing a memory area. The method includes jumping from a destination address to a source address, reading a data word at the source address after jumping to the source address, and examining the data word. The source address was determined based on a static test.

Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range.

Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells.

Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells. The processor is configured to test memory cells of a protected memory area of the memory by performing memory accesses at bit level, control a counting register in such a way that a value stored in the counting register is modified according to a number of performed memory accesses, and test memory cells of the protected memory area of the memory only if the value stored in the counting register lies within a permissible value range.

Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.

Abstract: A method for testing memory cells under test of an integrated circuit includes allocating an access value to a memory access and granting an access credit. If the access value of the memory access does not exceed the access credit, the memory access is performed and the access credit is reduced by the access value. The memory access is performed to one memory cell or at bit level to a plurality of memory cells. A processor is connectable to a memory having a plurality of memory cells.

Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.

Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.

Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.

Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.

Abstract: Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state representation of a first plurality of state representations and a second memory cell configured to selectively take on at least one of a second plurality of state representations. The second plurality of state representations is different than the first plurality of state representations. An apparatus includes a processing unit and a memory unit coupled to the processing unit. The memory unit includes a sector of memory cells. Further disclosed are a method of operating a memory unit sector and a method of controlling a sector of a memory unit.

Abstract: A circuitry for error-correcting data and for checking a correctness of an error-correction capability of an error-correction component of the circuitry is provided. The circuitry includes an input interface for receiving an input data word. Moreover, the circuitry includes a data manipulator for manipulating one or more bits of a test data word to obtain a modified data word, wherein said test data word is said input data word or is derived from said input data word. Furthermore, the circuitry includes said error-correction component for processing the modified data word. Moreover, the circuitry includes an evaluation component for evaluating the correctness of the error-correction capability of the error-correction component depending on the processing of the modified data word by the error-correction component.

Abstract: The invention provides a buffer circuit for a memory module including at least one configuration register bank for storing configuration data of the memory module, an error check logic for performing an error check of input signals applied to the memory module via input pins of the memory module to generate a signature output by the memory module via at least one output pin of the memory module, and a controller which depending on an output request setting stored in a configuration register of the configuration register bank reads out information data the buffer circuit via the output pin of the memory module.

Abstract: The invention provides a buffer circuit for a memory module comprising at least one configuration register bank for storing configuration data of said memory module, an error check logic for performing an error check of input signals applied to the memory module via input pins of said memory module to generate a signature output by said memory module via at least one output pin of said memory module, and a controller which depending on an output request setting stored in a configuration register of said configuration register bank reads out information data said buffer circuit via said output pin of said memory module.

Abstract: An electronic memory apparatus has a plurality of memory devices, a plurality of temperature sensors and a control unit. The memory devices each have a multiplicity of nonvolatile memory cells that are refreshed during operation of the electronic memory apparatus. The control unit passes a same periodic clock signal to each of the memory devices. The clock signal causes the memory cells to be refreshed in the memory devices. Each temperature sensor is associated with a respective memory device and measures a local temperature near the respective memory device during operation. Each memory device individually determines, on the basis of the temperature measured by the temperature sensor that is assigned to it, how many of its memory cells are simultaneously refreshed when memory cells are being refreshed.

Abstract: A nonvolatile memory cell (1) can be integrated in space-saving fashion into a semiconductor circuit (10) intended for volatile storage with the aid of volatile memory cells (2). The memory cell (1) has a programmable component (3) having an electrical resistance that can be altered by reprogramming, and also first (8) and second switching elements (9), which switch a first current path (J1) or a second current path (J2) in conducting fashion upon activation of optionally a first (11) or a second word line (12). At least one of the two current paths leads via the programmable component (3). Potentials of two bit lines (21, 22) to which the memory cell (1) according to the invention is connected can be altered as a result of the first or the second current path (J1, J2) being activated temporarily. The memory cell (1) permanently stores an item of digital information and can be driven by word lines (11, 12) and bit lines (21, 22) such as are conventionally used in volatile semiconductor memories (10).

Abstract: A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same loads during manufacturing and test processes, and that at least one regular memory cell from a regular memory area and at least one redundant memory cell from a redundant memory area are connected with each other via a coupling circuit. The coupling circuit, in particular during the testing of the operability of the semiconductor memory device or of the memory cells, respectively, determines the state of the regular memory cell and/or the redundant memory cell. Thus, in tested and repaired semiconductor memory devices, so-called redundancy storage space for the repair of defective memory capacity can be provided for repair even in the last memory test step, including full test severity and fulfilling all and any reliability requirements for the repair of high-grade memory devices.

Abstract: An integrated semiconductor memory includes a memory cell array having memory cells for storing a datum having a first and a second data value. An input datum present at a data terminal is stored multiply in the memory cells of the memory cell array. In order to read out the input datum, the multiply stored input data are fed to an evaluation circuit. The evaluation circuit generates, on the output side, an output datum having the data value that was stored more frequently in the memory cells used for multiple storage of the input datum than other data values. The integrated semiconductor memory thus makes it possible to reduce transfer errors when reading data into the memory cell array or reading data out of the memory cell array.

Abstract: An integrated semiconductor memory device includes a control circuit with a mode register to store operating parameters, as well as further registers to store further operating parameters. An operating parameter is selectively written to or read from one of the registers for storage of an operating parameter as a function of a first or second state of a configuration signal that is applied to an address connection. Any subsequent write and read access to one of the registers for storage of an operating parameter takes place analogously to a write and read access to a memory cell in a memory cell array. The integrated semiconductor memory device is thus operated to allow writing and reading of operating parameters using a standard interface and a standard protocol for inputting and outputting data to and from the memory cell array.