Abstract: A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.

Abstract: In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.

Abstract: Sigma-delta converters having a sampling circuit are provided. The sampling circuit is actuated such that sampling times are at least partially random.

Abstract: In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.

Abstract: A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.

Abstract: Devices for sampling a plurality of input signals are provided, wherein a sampling device is controlled to sample the input signals in a random order with additional delays. Other embodiments relate to voltage monitoring systems and corresponding methods.

Abstract: Sigma-delta converters having a sampling circuit are provided. The sampling circuit is actuated such that sampling times are at least partially random.

Abstract: Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.

Abstract: A circuit (100) comprises an input terminal (141) which is configured to receive an analog input signal (142). The circuit (100) also comprises a combination element (601) which is configured to combine a number of time-displaced signal values of the input signal (142) to form an analog combination signal (144). The circuit (100) also comprises a quantizer (131) having a converter core which is configured to receive the combination signal (144) via passive charge redistribution from the combination element (601) and to convert it into a digital output signal (145). Such techniques can thus provide for an analog/digital conversion with filtering in the analog domain.

Abstract: Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.

Abstract: A circuit (100) comprises an input terminal (141) which is configured to receive an analog input signal (142). The circuit (100) also comprises a combination element (601) which is configured to combine a number of time-displaced signal values of the input signal (142) to form an analog combination signal (144). The circuit (100) also comprises a quantizer (131) having a converter core which is configured to receive the combination signal (144) via passive charge redistribution from the combination element (601) and to convert it into a digital output signal (145). Such techniques can thus provide for an analog/digital conversion with filtering in the analog domain.

Abstract: In some examples, a method includes controlling a first set of switches to deliver a first voltage signal through a first set of capacitors to a common node. The method also includes controlling a second set of switches to deliver a second voltage signal through a second set of capacitors to the common node, wherein the first set of capacitors is electrically connected to the second set of capacitors by the common node. The method further includes measuring a time duration to discharge the common node. The second voltage signal includes an opposing polarity to the first voltage signal.

Abstract: Devices for sampling a plurality of input signals are provided, wherein a sampling device is controlled to sample the input signals in a random order with additional delays. Other embodiments relate to voltage monitoring systems and corresponding methods.