Patents by Inventor Martin Polzl
Martin Polzl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230230903Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.Type: ApplicationFiled: December 21, 2022Publication date: July 20, 2023Applicant: Infineon Technologies AGInventors: Hooi Boon TEOH, Hao ZHUANG, Oliver BLANK, Paul Armand CALO, Markus DINKEL, Josef Höglauer, Daniel Hölzl, Wee Aun JASON LIM, Gerhard Thomas Nöbauer, Ralf OTREMBA, Martin Pölzl, Ying Pok SAM, Xaver Schlögel, Chee Voon TAN
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Patent number: 10438945Abstract: A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.Type: GrantFiled: September 19, 2017Date of Patent: October 8, 2019Assignee: Infineon Technologies Austria AGInventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
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Patent number: 9978862Abstract: A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal.Type: GrantFiled: April 30, 2013Date of Patent: May 22, 2018Assignee: Infineon Technologies Austria AGInventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
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Publication number: 20180047719Abstract: A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.Type: ApplicationFiled: September 19, 2017Publication date: February 15, 2018Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
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Patent number: 9431392Abstract: A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.Type: GrantFiled: March 15, 2013Date of Patent: August 30, 2016Assignee: Infineon Technologies Austria AGInventors: Walter Rieger, Hans Weber, Michael Treu, Gerhard Nöbauer, Martin Pölzl, Martin Vielemeyer, Franz Hirler
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Publication number: 20150014858Abstract: A semiconductor die includes a semiconductor body, a transistor device disposed in the semiconductor body and having a gate, a source and a drain, and a sense device disposed in the semiconductor body and operable to sense a parameter associated with the transistor device. The die further includes a source pad at a first side of the semiconductor body and electrically connected to the source of the transistor device, a drain pad at a second side of the semiconductor body opposing the first side and electrically connected to the drain of the transistor device, and a sense pad at the second side of the semiconductor body and spaced apart from the drain pad. The sense pad is electrically connected to the sense device. A corresponding package and method of manufacturing are also disclosed.Type: ApplicationFiled: July 11, 2013Publication date: January 15, 2015Inventors: Ralf Otremba, Josef Höglauer, Gerhard Nöbauer, Martin Pölzl
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Publication number: 20140346569Abstract: A semiconductor die includes a III-nitride semiconductor substrate, a power HEMT (high-electron-mobility transistor) disposed in the III-nitride semiconductor substrate, and a first gate driver HEMT monolithically integrated with the power HEMT in the III-nitride semiconductor substrate. The power HEMT and the first gate driver HEMT each have a gate, a source and a drain. The first gate driver HEMT logically forms part of a driver, and is electrically connected to the gate of the power HEMT. The first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device. Additional embodiments of semiconductor dies and methods of manufacturing are also described.Type: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
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Publication number: 20140319602Abstract: A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal.Type: ApplicationFiled: April 30, 2013Publication date: October 30, 2014Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
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Publication number: 20140264577Abstract: A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Walter Rieger, Hans Weber, Michael Treu, Gerhard Nöbauer, Martin Pölzl, Martin Vielemeyer, Franz Hirler
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Patent number: 7250343Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).Type: GrantFiled: November 12, 2004Date of Patent: July 31, 2007Assignee: Infineon Technologies AGInventors: Manfred Kotek, Oliver Häberlen, Martin Pölzl, Walter Rieger
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Patent number: 7186618Abstract: When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.Type: GrantFiled: October 29, 2004Date of Patent: March 6, 2007Assignee: Infineon Technologies AGInventors: Martin Pölzl, Franz Hirler, Oliver Häberlen, Manfred Kotek, Walter Rieger
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Patent number: 7005351Abstract: A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.Type: GrantFiled: March 19, 2003Date of Patent: February 28, 2006Assignee: Infineon Technologies AGInventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Pölzl, Heimo Hofer
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Patent number: 6927101Abstract: A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zone, and at least one control electrode adjacent the channel zone. The control electrode is insulated from the semiconductor body. A second terminal zone of the first conduction type is fabricated in the channel zone near the front side of the semiconductor body by: doping the channel zone near the front side with a first dopant concentration to fabricate a first zone of the first conduction type, and doping a section of the first zone with a second dopant concentration higher than the first dopant concentration to form a second zone of the first conduction type.Type: GrantFiled: March 28, 2003Date of Patent: August 9, 2005Assignee: Infineon Technologies AGInventors: Ralf Henninger, Franz Hirler, Martin Pölzl, Walter Rieger
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Publication number: 20050151190Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).Type: ApplicationFiled: November 12, 2004Publication date: July 14, 2005Applicant: Infineon Technologies AGInventors: Manfred Kotek, Oliver Haberlen, Martin Polzl, Walter Rieger
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Publication number: 20050145936Abstract: When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.Type: ApplicationFiled: October 29, 2004Publication date: July 7, 2005Applicant: Infineon Technologies AGInventors: Martin Polzl, Franz Hirler, Oliver Haberlen, Manfred Kotek, Walter Rieger
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Patent number: 6891223Abstract: Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.Type: GrantFiled: March 19, 2003Date of Patent: May 10, 2005Assignee: Infineon Technologies AGInventors: Joachim Krumrey, Franz Hirler, Ralf Henninger, Martin Pölzl, Walter Rieger
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Patent number: 6806533Abstract: A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate, which is formed in a trench, with a distance between the trench of the edge cell and the trench of the immediately adjacent transistor cell being less than the distance between a trench of a transistor cell and the trench of an immediately adjacent transistor cell in the cell array.Type: GrantFiled: March 28, 2003Date of Patent: October 19, 2004Assignee: Infineon Technologies AGInventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Markus Zundel, Walter Rieger, Martin Pölzl
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Publication number: 20040031987Abstract: A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.Type: ApplicationFiled: March 19, 2003Publication date: February 19, 2004Inventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Polzl, Heimo Hofer
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Publication number: 20030209757Abstract: A semiconductor component has a cell array formed in a semiconductor body with a number of identical transistor cells and at least one edge cell formed at an edge of the cell array. Each of the transistor cells has a control electrode, which is formed in a trench, and the edge cell has a field plate, which is formed in a trench, with a distance between the trench of the edge cell and the trench of the immediately adjacent transistor cell being less than the distance between a trench of a transistor cell and the trench of an immediately adjacent transistor cell in the cell array.Type: ApplicationFiled: March 28, 2003Publication date: November 13, 2003Inventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Markus Zundel, Walter Rieger, Martin Polzl
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Publication number: 20030186507Abstract: A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zone, and at least one control electrode adjacent the channel zone. The control electrode is insulated from the semiconductor body. A second terminal zone of the first conduction type is fabricated in the channel zone near the front side of the semiconductor body by: doping the channel zone near the front side with a first dopant concentration to fabricate a first zone of the first conduction type, and doping a section of the first zone with a second dopant concentration higher than the first dopant concentration to form a second zone of the first conduction type.Type: ApplicationFiled: March 28, 2003Publication date: October 2, 2003Inventors: Ralf Henninger, Franz Hirler, Martin Polzl, Walter Rieger