Patents by Inventor Martin Ranke

Martin Ranke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to perform full accuracy hierarchical block level timing analysis with parameterized chip level contexts
    Patent number: 10423742
    Abstract: A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: September 24, 2019
    Assignee: Synopsys, Inc.
    Inventors: Qiuyang Wu, Martin Ranke, Min Li
  • Method to Perform Full Accuracy Hierarchical Block Level Timing Analysis with Parameterized Chip Level Contexts
    Publication number: 20180210986
    Abstract: A method and apparatus for on chip variation path-based pessimism reduction and improving analysis of a hierarchical integrated circuit design in an electrical circuit. The circuit has one or more block circuit levels and a top circuit level. The method in one embodiment comprises characterizing the top circuit level to produce a context function, the context function used by the block circuit level for evaluation.
    Type: Application
    Filed: January 24, 2017
    Publication date: July 26, 2018
    Inventors: Qiuyang Wu, Martin Ranke, Min Li