Abstract: Faulty memory cells in a plurality of memory blocks are replaced by redundant memory cells. Each block includes plurality of first and second redundant address lines with assigned memory cells. The first redundant address lines of a block can be used in at least one other memory block. A fault image is determined and the memory is reconfigured so as to replace faulty memory cells. If one or more first redundant address lines with faulty memory cells have been displaced from one block to another block, the displaced first redundant address line with faulty memory cells is assigned to the other block. It is then determined whether the fault image is covered by the reconfiguration taking account of the assignment. If the fault image is covered, the reconfiguration is output as a valid solution.

Abstract: In a device and a method associating information concerning first memory cells and second memory cells of a memory element with an external memory, with each address of the memory element having a first predetermined number of memory cells associated therewith and each address of the external memory having a second number of memory cells associated therewith that is greater than said first predetermined number, and with said second predetermined number of memory cells on each address of the external memory being adapted to be subdivided into a first group of memory cells and a second group of memory cells, an input receives the information concerning said first and second memory cells. The information concerning first memory cells is assigned to the first group of memory cells in the external memory, and the information concerning the second memory cells is associated to the second group of memory cells in the external memory.

Abstract: In a device and a method associating information concerning first memory cells and second memory cells of a memory element with an external memory, with each address of the memory element having a first predetermined number of memory cells associated therewith and each address of the external memory having a second number of memory cells associated therewith that is greater than said first predetermined number, and with said second predetermined number of memory cells on each address of the external memory being adapted to be subdivided into a first group of memory cells and a second group of memory cells, an input receives the information concerning said first and second memory cells. The information concerning first memory cells is assigned to the first group of memory cells in the external memory, and the information concerning the second memory cells is associated to the second group of memory cells in the external memory.

Abstract: In a memory, faulty memory cells in a plurality of memory blocks are replaced by redundant memory cells. Each block comprises a plurality of first and second regular address lines with assigned memory cells and a plurality of first and second redundant address lines with assigned memory cells, through which the first and second regular address lines are replaceable. The first redundant address lines of a block are utilizable in at least one other memory block, faulty memory cells of the first redundant address lines displaced to another block being replaceable by second redundant address lines of the other block. According to the method for reconfiguring the memory, a fault image is determined and the memory is reconfigured so as to replace faulty memory cells. It is then determined whether at least one first redundant address line with faulty memory cells has been displaced from one block to another block by the reconfiguration.

Abstract: The high frequency oscillator comprises a reference oscillator, a phase-locked loop circuit with a phase frequency detector, a charge pump, a ring oscillator and a divider, the reference oscillator being coupled to the phase frequency detector for frequency control. The ring oscillator is a symmetrical delay cell oscillator containing two amplifiers with a dual output stage for providing I/Q output signal generation. The reference oscillator works in the range of 1.25-1.5 GHz and is a Colpitts type digital controlled frequency synthesizer with an external tank circuit for providing a low phase noise, and the dividing factor of the divider is four for providing a tuned output range of 5 to 6 GHz. The phase-locked loop circuit is integrated together with the reference oscillator into an integrated circuit, using advantageously a BICMOS Silicon/Germanium process, which is well suited for RF applications.

Abstract: Electronic circuits test memory matrices that have address inputs, data outputs and a memory matrix. The memory spaces in the memory matrix can be addressed via the address inputs, and output a data item via the data outputs. The circuit also has an output circuit, which connects to at least one of the address inputs, to the memory matrix, and to the data outputs. The output circuit outputs a data item to different data outputs, depending on its address. This circuit can be operated in an apparatus for testing the function of a memory matrix, with the circuit connecting the test apparatus and a memory matrix to one another such that the outputs of the memory matrix are produced at the data inputs of the circuit, and the data outputs together with the further data output of the circuit are applied to inputs of the test apparatus.

Abstract: Electronic circuits test memory matrices that have address inputs, data outputs and a memory matrix. The memory spaces in the memory matrix can be addressed via the address inputs, and output a data item via the data outputs. The circuit also has an output circuit, which connects to at least one of the address inputs, to the memory matrix, and to the data outputs. The output circuit outputs a data item to different data outputs, depending on its address. This circuit can be operated in an apparatus for testing the function of a memory matrix, with the circuit connecting the test apparatus and a memory matrix to one another such that the outputs of the memory matrix are produced at the data inputs of the circuit, and the data outputs together with the further data output of the circuit are applied to inputs of the test apparatus.

Abstract: The high frequency oscillator comprises a reference oscillator, a phase-locked loop circuit with a phase frequency detector, a charge pump, a ring oscillator and a divider, the reference oscillator being coupled to the phase frequency detector for frequency control. The ring oscillator is a symmetrical delay cell oscillator containing two amplifiers with a dual output stage for providing I/Q output signal generation. The reference oscillator works in the range of 1,25-1,5 GHz and is a Colpitts type digital controlled frequency synthesizer with an external tank circuit for providing a low phase noise, and the dividing factor of the divider is four for providing a tuned output range of 5 to 6 GHz. The phase-locked loop circuit is integrated together with the reference oscillator into an integrated circuit, using advantageously a BICMOS Silicon/Germanium process, which is well suited for RF applications.

Abstract: The upconverter mixer circuit comprises a Gilbert cell with an LC-resonator tuned to the output frequency of the upconverter mixer circuit, and an output buffer. In a preferred embodiment the output buffer comprises a differential amplifier being emitter degenerated with inductances for a low-pass characteristic. The LC-resonator of the Gilbert cell as well as the inductances of the output amplifier are integrated in an integrated circuit together with the other parts of the upconverter mixer circuit and provide a first selection within the integrated circuit for the subsequent stages, for example an intermediate frequency filter of a double conversion TV tuner. When the upconverter mixer circuit is operated with a strong DC-current and hard switching, which is necessary for achieving low noise, strong high frequency parasitic currents are also generated.

Abstract: The reduction of interfering influences in an LC resonant circuit with an integrated circuit is effected by including the interfering elements of the housing in the resonant circuit. This precludes the occurrence of parasitic radio-frequency oscillation modes. It also ensures good radio-frequency properties and a wide frequency tuning range.

Abstract: A multiplying amplifier which is controlled in a dB linear manner. Transistors, having a numerical distribution coeffient and having the output voltage to be dB-linearly dependent responsive to a control voltage, are connected to the inputs of a muliplier.

Abstract: An arrangement for reducing interference in tuned circuits in integrated circuits as a result of the reception and transmission of high frequencies. An external tuned circuit is integrated in the integrated circuit and the interference which is otherwise produced by the connecting pins is eliminated.

Abstract: A radio-frequency (RF) receiver generally contains an RF amplifier, a mixer stage, a mixer oscillator, a demodulator and an AGC (automatic gain control) circuit, to which the output voltage of the demodulator and a set voltage value for the automatic gain control are applied. Such RF receivers have a non-optimal signal-to-noise ratio under certain circumstances. The present invention improves the signal-to-noise ratio in such high frequency receivers, as well as the effectiveness of the AFT (automatic fine tuning) circuit. The amplitude of the AGC set voltage value is regulated depending on the frequency of the received RF signal so that the mixer stage is optimally controlled at all frequencies of the RF signal. In one embodiment, a PLL circuit connected to the output of the intermediate frequency amplifier to regenerate the non-modulated image carrier, is further used to ensure automatic fine tuning by regulating the frequency of the mixer oscillator.

Abstract: For the purpose of a high precision frequency fine tuning, for example, to a certain television channel, an analog circuit, the frequency of which can be balanced, for example, an demodulator, is balanced in an integrated circuit with the help of a control current. The control current generated in a regulating loop is dependent on a reference frequency with the appropriate accuracy and on a reference frequency with the appropriate accuracy and on a reference capacitancy integrated on the chip. After selecting a frequency, the analog circuit is calibrated and the frequency is subsequently fine-tuned in a measuring mode. Following that, the analog circuit operates in the normal mode.

Abstract: To improve the regulation (gain control) characteristics of a controllable amplifier, a negative feedback network in a differential amplifier is subdivided into individual networks supplied each with its own control current. In order to reduce distortion caused by non-linear sections contained in the networks or to increase intermodulation resistance, the individual control currents are reduced with an increasing input voltage. To obtain a dB-linear regulation characteristic the control currents may be proportioned, for example, in accordance with tangential-hyperbolic characteristic curves.

Abstract: A universal filter is provided with three inputs Vh, Vb and V1, with one output Vout, with two transconductance amplifiers Gm1, Gm2, with four capacitors mCO, (1-m)CO, CO and LCO and an amplifier K as well as a voltage follower VF. Depending on the connections of the three inputs, the universal filter takes the form of a high-pass or low-pass or band-pass filter or a trap filter or an all-pass or an otherwise active filter. Advantageously, by selection of parameters (e.g., trans-conductance, gain, scaling), the various filter characteristics like quality (Q), slope, median frequency, amplification, etc., may be adjusted. A further advantage is that the low component count of the filter provides improved reliability, reduced cost and facilitates efficient and economic fabrication in discrete or integrated circuit form.

Abstract: An FM detector for demodulating frequency modulated signals includes an FM detector having an oscillator composed of a capacitor and a Schmitt Trigger. The oscillator is controlled by the input signal to the FM detector. The FM detector also includes a phase detector for mixing the input signal with an oscillator signal from the oscillator to provide an output signal. The frequency of the oscillator is set to the frequency of the input signal using components internal to the FM detector. A first switch is used to charge and discharge the capacitor in accordance with the state of the Schmitt Trigger. A second switch is used to set the frequency of the oscillator to the frequency of the input signal.